-- Model Name : Serial to Parallel Converter -- Author : Zainalabedin Navabi -- Last Updated : 09 / 15 / 1996 -- This document is © copyrighted by the Author.
ENTITY serial2parallel IS GENERIC (bps : INTEGER); PORT (serial, received : IN BIT; dataready : BUFFER BIT; overrun, frame_error : OUT BIT; parallel_out : BUFFER BIT_VECTOR (7 DOWNTO 0)); END serial2parallel; -- ARCHITECTURE waiting OF serial2parallel IS BEGIN collect : PROCESS VARIABLE buff : BIT_VECTOR (7 DOWNTO 0); CONSTANT half_bit : TIME := (1000000.0/REAL(bps))/2.0 * 1 US; CONSTANT full_bit : TIME := (1000000.0/REAL(bps)) * 1 US; BEGIN WAIT UNTIL serial = '0'; WAIT FOR half_bit; FOR count IN 0 TO 7 LOOP WAIT FOR full_bit; buff (count) := serial; END LOOP; WAIT FOR full_bit; IF serial = '0' THEN frame_error <= '1'; WAIT UNTIL serial = '1'; ELSE frame_error <= '0'; dataready <= '1'; parallel_out <= buff; WAIT UNTIL received = '1'; WAIT UNTIL received = '0'; dataready <= '0'; END IF; END PROCESS collect; -- too_fast : PROCESS BEGIN IF dataready = '1' THEN WAIT UNTIL serial = '0'; IF dataready = '1' THEN overrun <= '1'; END IF; ELSE overrun <= '0'; END IF; WAIT ON dataready; END PROCESS too_fast; END waiting; |
ENTITY tester IS END tester; -- ARCHITECTURE io OF tester IS CONSTANT rate : INTEGER := 9600; CONSTANT fb : TIME := (1000000.0/REAL(rate)) * 1 US; SIGNAL serial, received : BIT; SIGNAL dataready, overrun, frame_error : BIT; SIGNAL parallel_out : BIT_VECTOR (7 DOWNTO 0); BEGIN s2p : ENTITY WORK.serial2parallel (waiting) GENERIC MAP (rate) PORT MAP (serial, received, dataready, overrun, frame_error, parallel_out); serial <= '1', '0' AFTER 2*fb, '1' AFTER 3*fb, '0' AFTER 4*fb, '1' AFTER 06*fb, '0' AFTER 20*fb, '1' AFTER 23*fb, '0' AFTER 25*fb, '1' AFTER 26*fb, '0' AFTER 27*fb, '1' AFTER 28*fb, '0' AFTER 33*fb; received <= '0', '1' AFTER 1.6 MS, '0' AFTER 1.6001 MS, '1' AFTER 3.5 MS, '0' AFTER 3.5001 MS; END io; |