-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 4.1 



-- ENTITIY DECLERATION OF INVERTER :

ENTITY inv IS
  PORT (i1 : IN BIT; o1 : OUT BIT);
END inv;
--



-- ARCHITECTURAL BODY OF INVERTER :

ARCHITECTURE single_delay OF inv IS
BEGIN
  o1 <= NOT i1 AFTER 4 NS;
END single_delay;
--