-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 4.4 



-- ENTITIY DECLERATION OF TWO-INPUT NAND :

ENTITY nand2 IS
  PORT (i1, i2 : IN BIT; o1 : OUT BIT);
END nand2;
--


-- ARCHITECTURE BODY OF TWO-INPUT NAND :

ARCHITECTURE single_delay OF nand2 IS
BEGIN
  o1 <= i1 NAND i2 AFTER 5 NS;
END single_delay;
--