-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 4.17 & 4.19 




-- ENTITIY DECLERATION OF NIBBLE COMPARATOR :

ENTITY nibble_comparator IS
  PORT (a, b : IN BIT_VECTOR (3 DOWNTO 0);  -- a and b data inputs
        gt,                                 -- previous greater than
        eq,                                 -- previous equal
        lt : IN BIT;                        -- previous less than
        a_gt_b,                             -- a > b
        a_eq_b,                             -- a = b
        a_lt_b : OUT BIT);                  -- a < b
END nibble_comparator;
--



-- ITERATIVE ARCHITECTURE OF NIBBLE COMPARATOR :

ARCHITECTURE iterative OF nibble_comparator IS
  COMPONENT comp1
    PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
  END COMPONENT;
  FOR ALL : comp1 USE ENTITY WORK.bit_comparator (gate_level);
  SIGNAL im : BIT_VECTOR ( 0 TO 8);
BEGIN
  c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
  c1to2: FOR i IN 1 TO 2 GENERATE
    c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), 
                       im(i*3+0), im(i*3+1), im(i*3+2) );
  END GENERATE;
  c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8), 
                      a_gt_b, a_eq_b, a_lt_b);

END iterative;
--