-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 4.29 




-- ENTITIY DECLERATION OF SET-RESET LATCH :

ENTITY sr_flipflop IS PORT (s, r, c : IN BIT; q : OUT BIT);
END sr_flipflop;
--



-- ARCHITECTURE BODY OF SR-LATCH :

ARCHITECTURE gate_level OF sr_latch IS
   COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
   FOR g1, g3 : n2 USE ENTITY WORK.nand2 (fast_single_delay);
   FOR g2, g4 : n2 USE ENTITY WORK.nand2 (single_delay);
   SIGNAL im1, im2, im3, im4 : BIT;
BEGIN  
   g1 : n2 PORT MAP (s, c, im1); 
   g2 : n2 PORT MAP (r, c, im2); 
   g3 : n2 PORT MAP (im1, im4, im3);
   g4 : n2 PORT MAP (im3, im2, im4);
   q <= im3;
END gate_level;
--