-- Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
-- FIGURE 5.22
-- ENTITY DECLERATION OF BIT COMPARATOR :
ENTITY bit_comparator IS
PORT (a, b, -- data inputs
gt, -- previous greater than
eq, -- previous equal
lt : IN BIT; -- previous less than
a_gt_b, -- greater
a_eq_b, -- equal
a_lt_b : OUT BIT); -- less than
END bit_comparator;
--
-- ASSOCIATING FIXED VALUES WIHT THE GENERICS OF THE LOGIC GATES :
ARCHITECTURE fixed_delay OF bit_comparator IS
COMPONENT n1
GENERIC (tplh, tphl : TIME);
PORT (i1: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n2
GENERIC (tplh, tphl : TIME);
PORT (i1, i2: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n3
GENERIC (tplh, tphl : TIME);
PORT (i1, i2, i3: IN BIT; o1: OUT BIT);
END COMPONENT;
FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay);
FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay);
FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (a, im1);
g1 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (b, im2);
g2 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, im2, im3);
g3 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, gt, im4);
g4 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im2, gt, im5);
g5 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im1, im2, eq, im6);
g7 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (a, b, eq, im7);
g8 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im6, im7, a_eq_b);
-- a_lt_b output
g9 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, b, im8);
g10 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, lt, im9);
g11 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (b, lt, im10);
g12 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im8, im9, im10, a_lt_b);
END fixed_delay;
--