-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 5.43 




-- ENTITY DECLERATION OF N-BIT D-LATCH :

ENTITY d_register IS 
  PORT (d : IN BIT_VECTOR (7 DOWNTO 0); c : IN BIT; 
        q : OUT BIT_VECTOR (7 DOWNTO 0) );
END d_register;
--



-- UNBOUND VHDL DESCRIPTION FOR AN N-BIT D-LATCH :

USE WORK.ALL;
ARCHITECTURE latch_based OF d_register IS
  COMPONENT dl PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT;
BEGIN  
  d8 : FOR i IN d'RANGE GENERATE
    di : dl PORT MAP (d(i), c, q(i));
  END GENERATE;
END latch_based;
--