-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 5.18 




-- ENTITY DECLARATION OF INVERTER :

ENTITY inv_t IS
  GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS);
  PORT (i1 : IN BIT; o1 : OUT BIT);
END inv_t;
--

-- AVERAGE-DELAY ARCHITECTURE OF INVERTER :

ARCHITECTURE average_delay OF inv_t IS
BEGIN
  o1 <= NOT i1 AFTER  (tplh + tphl) / 2;
END average_delay;







-- ENTITY DECLARATION OF 2-INPUT NAND GATE :

ENTITY nand2_t IS
  GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS);
  PORT (i1, i2 : IN BIT; o1 : OUT BIT);
END nand2_t;
--

-- AVERAGE-DELAY ARCHITECTURE OF 2-INPUT NAND GATE :

ARCHITECTURE average_delay OF nand2_t IS
BEGIN
  o1 <= i1 NAND i2 AFTER  (tplh + tphl) / 2;
END average_delay;







-- ENTITY DECLARATION OF 3-INPUT NAND GATE :

ENTITY nand3_t IS
  GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS);
  PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT);
END nand3_t;
--

-- AVERAGE-DELAY ARCHITECTURE OF 3-INPUT NAND GATE :

ARCHITECTURE average_delay OF nand3_t IS
BEGIN
  o1 <= NOT ( i1 AND i2 AND i3 ) AFTER  (tplh + tphl) / 2;
END average_delay;
--