-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 5.41 




-- ENTITY DECLERATION OF SR-LATCH :

ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT);
END sr_latch;
--



-- UNBOUND VHDL DESCRIPTION FOR AN SR-LATCH :

ARCHITECTURE gate_level OF sr_latch IS
  COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
  SIGNAL im1, im2, im3, im4 : BIT;
BEGIN  
   g1 : n2 PORT MAP (s, c, im1); 
   g2 : n2 PORT MAP (r, c, im2); 
   g3 : n2 PORT MAP (im1, im4, im3);
   g4 : n2 PORT MAP (im3, im2, im4);
   q <= im3;
END gate_level;
--