-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 5.48 




-- ENTITY DECLERATION OF SINGLE DELAY D-REGISTER TEST BENCH :

ENTITY d_register_test_bench IS
END d_register_test_bench ;
--



-- TEST BENCH FOR THE SINGLE DELAY D-REGISTER :

ARCHITECTURE single OF d_register_test_bench IS
  COMPONENT reg PORT (d : IN BIT_VECTOR (7 DOWNTO 0); c : IN BIT; 
                      q : OUT BIT_VECTOR (7 DOWNTO 0) );
  END COMPONENT;
  FOR r8 : reg USE CONFIGURATION WORK.single_gate_delay;
  SIGNAL data, outdata : BIT_VECTOR (7 DOWNTO 0); 
  SIGNAL clk : BIT;
BEGIN
  r8: reg PORT MAP (data, clk, outdata);
  data <= X"00", X"AA" AFTER 0500 NS, X"55" AFTER 1500 NS;
  clk <= '0', '1' AFTER 0200 NS, '0' AFTER 0300 NS,
              '1' AFTER 0700 NS, '0' AFTER 0800 NS,
              '1' AFTER 1700 NS, '0' AFTER 1800 NS;
END single;
--