-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 9.34 




-- DECLARATION OF PARWAN ALU UNIT :

LIBRARY cmos;
USE cmos.basic_utilities.ALL;
LIBRARY par_library;
USE par_library.par_utilities.ALL;
USE WORK.alu_operations.ALL;
--
ENTITY arithmatic_logic_unit IS
  PORT (a_side, b_side : IN byte; code : IN qit_vector (2 DOWNTO 0);
        in_flags : IN nibble; z_out : OUT byte;  out_flags : OUT nibble);
END arithmatic_logic_unit;
--


-- BEHAVIORAL DESCRIPTION OF PARWAN ALU UNIT :

ARCHITECTURE behavioral OF arithmatic_logic_unit IS
BEGIN
  coding: PROCESS (a_side, b_side, code)
    VARIABLE t : qit_vector (9 DOWNTO 0);
    VARIABLE v, c, z, n : qit;
    ALIAS n_flag_in : qit IS in_flags(0);
    ALIAS z_flag_in : qit IS in_flags(1);
    ALIAS c_flag_in : qit IS in_flags(2);
    ALIAS v_flag_in : qit IS in_flags(3);
  BEGIN
    CASE code IS
      WHEN a_add_b => 
        t := add_cv (b_side, a_side, c_flag_in);
        c := t(8);  v := t(9);  -- other flags are set at the end
      WHEN a_sub_b => 
        t := sub_cv (b_side, a_side, c_flag_in); 
        c := t(8);  v := t(9);
      WHEN a_and_b =>
        t (7 DOWNTO 0) := a_side AND b_side;
        c := c_flag_in;  v := v_flag_in;
      WHEN a_input  =>
        t (7 DOWNTO 0) := a_side;
        c := c_flag_in;  v := v_flag_in;
      WHEN b_input  =>
        t (7 DOWNTO 0) := b_side;
        c := c_flag_in;  v := v_flag_in;
      WHEN b_compl =>
        t (7 DOWNTO 0) := NOT b_side;
        c := c_flag_in;  v := v_flag_in;
      WHEN OTHERS => NULL;
    END CASE;
    n := t(7);
    z := set_if_zero (t);
    z_out <= t (7 DOWNTO 0);
    out_flags <= v & c & z & n;
  END PROCESS coding;
END behavioral;
--