-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 9.68 




-- A TEST BENCH FOR PARWANBEHAVIORAL AND DATAFLOW  DESCRIPTIONS :

ARCHITECTURE input_output OF parwan_tester IS
  COMPONENT parwan PORT (clk : IN qit;  interrupt : IN qit;
                         read_mem, write_mem : OUT qit; 
                         databus : INOUT wired_byte; adbus : OUT twelve );
  END COMPONENT;
  SIGNAL clock, interrupt, read, write : qit;
  SIGNAL data : wired_byte := "ZZZZZZZZ";
SIGNAL adr : INTEGER := 0;
  SIGNAL address : twelve;
  TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte;
BEGIN
  int : interrupt <= '1', '0' AFTER 4500 NS;
  clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock;
  cpu : parwan PORT MAP (clock, interrupt, read, write, data, address);
  mem : PROCESS 
    VARIABLE memory : byte_memory ( 0 TO 63 ) := 
      ("00000000", "00011000", "10100000", "00011001", --lda 24, sta 25
       "00100000", "00011010", "01000000", "00011011", --and 26, add 27
       "11100010", "11101001", "01100000", "00011100", --cac, asr, sub 28
       "00010000", "00011101", "11000000", "00100100", --lda i 29, jsr 36
       "11101000", "11100000", "10000000", "00100000", --asl, nop, jmp 32
       "00000000", "00000000", "00000000", "00000000",
       "01011100", "00000000", "01110000", "00010010", --(24, 25, 26, 27)
       "00001100", "00011111", "00000000", "01011010", --(28, 29, 30, 31)
       "10000000", "00010010", "00000000", "00000000", --jmp 18
       "00000000", "11100010", "10010000", "00100100", --   , cma, jmp i 36
       "00000000", "00000000", "00000000", "00000000",
       "00000000", "00000000", "00000000", "00000000",
       "00000000", "00000000", "00000000", "00000000",
       "00000000", "00000000", "00000000", "00000000",
       "00000000", "00000000", "00000000", "00000000",
       "00000000", "00000000", "00000000", "00000000" );
    VARIABLE ia : INTEGER;
  BEGIN
    WAIT ON read, write;
    qit2int (address, ia);
adr <= ia;
    IF read = '1' THEN 
      IF ia >= 64 THEN 
        data <= "ZZZZZZZZ";
      ELSE
        data <= wired_byte ( memory (ia) );
      END IF;
      WAIT UNTIL read = '0';
      data <= "ZZZZZZZZ";
    ELSIF write = '1' THEN
      IF ia < 64 THEN
        memory (ia) := byte ( data );
      END IF;
      WAIT UNTIL write = '0';
    END IF;
  END PROCESS mem;
END input_output;
--