-- Copyright © 1993 by  McGraw-Hill, Inc. and Zainalabedin Navabi

-- FIGURE 9.47 




-- ENTITY DECLARATION OF PARWAN DATA SECTION :

LIBRARY cmos;
USE cmos.basic_utilities.ALL;
LIBRARY par_library;
USE par_library.par_utilities.ALL;
--
ENTITY par_data_path IS
  PORT (databus : INOUT wired_byte BUS := "ZZZZZZZZ";  adbus : OUT twelve;
        clk : IN qit;
        -- register controls:
        load_ac, zero_ac, 
        load_ir, 
        increment_pc, load_page_pc, load_offset_pc, reset_pc,
        load_page_mar, load_offset_mar, 
        load_sr, cm_carry_sr, 
        -- bus connections:
        pc_on_mar_page_bus, ir_on_mar_page_bus, 
        pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
        pc_offset_on_dbus, obus_on_dbus, databus_on_dbus, 
        mar_on_adbus,
        dbus_on_databus,
        -- logic unit function control inputs:
        arith_shift_left, arith_shift_right : IN qit;
        alu_code : IN qit_vector (2 DOWNTO 0);
        -- outputs to the controller:
        ir_lines : OUT byte; status : OUT nibble
       );
END par_data_path;
--






-- FIGURE 9.48




-- DECLARATIVE PART OF PARWAN DATA STRUCTURAL ARCHITECTURE:

ARCHITECTURE structural OF par_data_path IS
  --
  COMPONENT ac 
    PORT (i8: IN byte; o8: OUT byte; load, zero, ck: IN qit);
  END COMPONENT;
  FOR r1: ac USE ENTITY WORK.accumulator_unit (dataflow);
  --
  COMPONENT ir 
    PORT (i8: IN byte; o8: OUT byte; load, ck: IN qit);
  END COMPONENT;
  FOR r2: ir USE ENTITY WORK.instruction_register_unit (dataflow);
   --
  COMPONENT pc 
    PORT (i12 : IN twelve; o12 : OUT twelve; 
          increment, load_page, load_offset, reset, ck : IN qit);
  END COMPONENT;
  FOR r3: pc USE ENTITY WORK.program_counter_unit (behavioral);
  --
  COMPONENT mar
    PORT (i12 : IN twelve; o12 : OUT twelve; 
          load_page, load_offset, ck : IN qit);
  END COMPONENT;
  FOR r4: mar USE ENTITY WORK.memory_address_register_unit (behavioral);
  --
  COMPONENT sr
    PORT (in_flags : IN nibble; out_status : OUT nibble;  
          load, cm_carry, ck : IN qit );
  END COMPONENT;
  FOR r5 : sr USE ENTITY WORK.status_register_unit (behavioral);
  --
  COMPONENT alu 
    PORT (a_side, b_side : IN byte; code : IN qit_vector; in_flags : IN nibble;
          z_out : OUT byte;  out_flags : OUT nibble);
  END COMPONENT;
  FOR l1 : alu USE ENTITY WORK.arithmatic_logic_unit (behavioral);
  --
  COMPONENT shu
    PORT (alu_side : IN byte; arith_shift_left, arith_shift_right : IN qit; 
          in_flags : IN nibble; obus_side : OUT byte;  out_flags : OUT nibble);
  END COMPONENT;
  FOR l2 : shu USE ENTITY WORK.shifter_unit (behavioral); 
  --
  SIGNAL ac_out, ir_out, alu_out, obus : byte;
  SIGNAL alu_a_inp : byte;
  SIGNAL pc_out, mar_out : twelve;
  SIGNAL dbus : wired_byte BUS;
  SIGNAL alu_flags, shu_flags, sr_out : nibble;
  SIGNAL mar_bus : wired_twelve BUS;
  SIGNAL mar_inp : twelve;







-- FIGURE 9.49





-- DECLARATIVE PART OF PARWAN DATA STRUCTURAL ARCHITECTURE (CNTD.):

BEGIN
  -- bus connections --
  --
  dbus1: alu_a_inp <= qit_vector (dbus);
  dbus2: BLOCK (dbus_on_mar_offset_bus = '1') 
    BEGIN  mar_bus (7 DOWNTO 0) <= GUARDED dbus; 
  END BLOCK dbus2;
  dbus3: BLOCK (dbus_on_databus = '1') 
    BEGIN  databus <= GUARDED dbus; 
  END BLOCK dbus3;
  --
  obus1: BLOCK (obus_on_dbus = '1') 
    BEGIN  dbus <= GUARDED wired_qit_vector (obus); 
  END BLOCK obus1;
  --
  databus1: BLOCK (databus_on_dbus = '1') 
    BEGIN  dbus <= GUARDED databus; 
  END BLOCK databus1;
  --
  mar_bus1: mar_inp <= qit_vector (mar_bus);
  --
  -- register connections --
  --
  r1: ac PORT MAP (obus, ac_out, load_ac, zero_ac, clk);
  --
  r2: ir PORT MAP (obus, ir_out, load_ir, clk);
  ir1: ir_lines <= ir_out;
  ir2: BLOCK (ir_on_mar_page_bus = '1')
  BEGIN 
    mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (ir_out (3 DOWNTO 0));
  END BLOCK ir2;
  --
  r3: pc PORT MAP (mar_out, pc_out, increment_pc, load_page_pc, load_offset_pc, reset_pc, clk);
  pc1: BLOCK (pc_on_mar_page_bus = '1') 
  BEGIN  
    mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (pc_out (11 DOWNTO 8));  
  END BLOCK pc1;
  pc2: BLOCK (pc_on_mar_offset_bus = '1') 
  BEGIN  
    mar_bus (7 DOWNTO 0) <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0));  
  END BLOCK pc2;
  pc3: BLOCK (pc_offset_on_dbus = '1') 
  BEGIN  
    dbus <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0));  
  END BLOCK pc3;
  --
  r4: mar PORT MAP (mar_inp, mar_out, load_page_mar, load_offset_mar, clk);
  mar1: BLOCK (mar_on_adbus = '1') 
    BEGIN  adbus <= GUARDED mar_out;  
  END BLOCK mar1;
  --  
  r5: sr PORT MAP (shu_flags, sr_out, load_sr, cm_carry_sr, clk);
  sr1: status <= sr_out;
  --
  -- connection of logical and register structures --
  --
  l1: alu PORT MAP (alu_a_inp, ac_out, alu_code, sr_out, alu_out, alu_flags);
  l2: shu PORT MAP (alu_out, arith_shift_left, arith_shift_right, alu_flags, obus, shu_flags); 
  
END structural;
--