PACKAGE concurrent_utilities IS
. . .
  SUBTYPE byte IS std_logic_vector (7 DOWNTO 0);
  TYPE byte_node;
  TYPE byte_node_ptr IS ACCESS byte_node;
  TYPE byte_node IS RECORD
    val    : byte;
    link   : byte_node_ptr; --for link list;  
  END RECORD;
  --
  --
END concurrent_utilities;



Figure 9.  Dynamic type declarations






LIBRARY work;
USE WORK.concurrent_utilities.ALL;
--
PACKAGE global_environment IS
  . . . 
  SHARED VARIABLE ir_out, . . . : byte_node_ptr:=NULL;
  SHARED VARIABLE databus, . . . byte_node_ptr:=NULL;
END global_environment;

Figure 10.  System buses and register outputs


ENTITY instruction_register_unit IS  PORT (load : IN …);
END instruction_register_unit;
--
ARCHITECTURE concurrent OF instruction_register_unit IS
BEGIN
  PROCESS (load)
    VARIABLE temp, temp2 : byte_node_ptr :=NULL;
  BEGIN
                -- first free
    WHILE (ir_out/=NULL AND ir_out/=zero_8) LOOP
      temp := ir_out;
      ir_out := ir_out.link;
      DEALLOCATE (temp);
    END LOOP; 
                -- allocate for the new data
    ir_out := NEW byte_node;
    ir_out.val := obus.val;
    temp  := obus.link;
    temp2 := ir_out;
    WHILE temp/=NULL LOOP
      temp2.link := NEW byte_node;
      temp2 := temp2.link;
      temp2.val := temp.val;
      temp := temp.link;
    END LOOP;
  END PROCESS;
END concurrent;


Figure 11.  Concurrent model of a simple register



ENTITY arithmetic_logic_unit IS
  PORT (code : IN …;  alu_operate : IN …);
END arithmetic_logic_unit;
--
ARCHITECTURE concurrent OF arithmetic_logic_unit IS
BEGIN
  coding: PROCESS (alu_operate)
    VARIABLE temp : std_logic_vector (9 DOWNTO 0);
    VARIABLE t, t1, a, b : byte_node_ptr:=NULL;
  BEGIN
  --********* free
    WHILE (alu_out/=NULL AND alu_out/=zero_8) LOOP
      t:=alu_out;
      alu_out:=alu_out.link;
      DEALLOCATE(t);
    END LOOP;
     CASE code IS
      WHEN a_add_b | a_sub_b => 
        a := dbus;
        b := ac_out;
        sr_t := sr_out;
        t1 := NEW byte_node;
        t:=t1;
        tf := NEW nibble_node;
        flags := tf;
        LOOP
          temp := addsub_cv (b.val, a.val, sr_t.val(2), code(1));
          t.val := temp(7 DOWNTO 0);
          . . .
          IF (a.link=NULL AND b.link=NULL) 
            THEN EXIT; END IF;
          IF (a.link/=NULL) THEN a:=a.link; END IF; 
          IF (b.link/=NULL) THEN b:=b.link; END IF;
          IF (sr_t.link/=NULL) THEN sr_t:=sr_t.link; END IF;
          t.link := NEW byte_node;
      END LOOP;
    END CASE;
  --*********** free t and the flags
END PROCESS coding;
END concurrent;

Figure 12.  ALU example



11100001 
11101000 
00010000 
00100111  --cla --asl --lda,i p1 --39
01010000 
00101000 
10110000 
00101001  --add,i p2 --40 --sta,i p3 --41
11100001 
11101000 
00000000 
00100111  --cla --asl --lda p1 --39
01000000 
00101010 
11100001 
11101000  --add #0 --42 --cla --asl
00000000 
00101000 
01000000 
00101010  --lda p2 --40 --add #0 --42
11100001 
11101000 
00000000 
00101001  --cla --asl --lda p3 --41
01000000 
00101010 
11100001 
11101000  --add #0 --42 --cla --asl
00000000 
00101011 
01100000 
00101100  --lda count --43 --sub #1 --44
11110010 
00100110 
10100000 
00101011  --bra_z  end --38 --sta count --43
10000000 
00000000 
11101111 
00101101  --jmp --00 --halt --p1 
00101110 
00101111 
00000000 
11111111  --p2 --p3 --#0 --count=255
00000001 
00000001 
00000010 
00000000  --#1 --data --data --data
00000000


11100001 cla --clr ac 
11101001 asl-- clear carry
00000000 lda 0:20
00010100 
01000000 add 0:21
00010101 
10100000 sta 0:22
00010110 
11101111 halt 
00000000 
00000000 
00000000 
00000000 
00000000 
00000000 
00000000 
00000000 
00000000 
00000000 
00000000 
00000001:00000001:00000001:00. . .
00000010:00000010:00000010:001: .  . 
00000011:00000011:00000011:001: .  .
00000000 
00000000 
00000000 
00000000 
00000000 
00000000 
00000000 

Figure 13.  a) Single and b)Bulk Data Representation in Memory