RASSP-Sanders Project - Synthesizable Dataflow - Arithmetic logic unit VHDL
-- Model Name : Synthesizable Dataflow - Arithmetic Logic Unit
-- Author : Zainalabedin Navabi
-- Last Updated : 09 / 15 / 1996
-- This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY parwan_s;
USE parwan_s.synthesis_parameters.ALL;
USE parwan_s.synthesis_utilities.ALL;
USE parwan_s.alu_operations.ALL;
--
ENTITY arithmetic_logic_unit IS
PORT (a_side, b_side : IN byte; code : IN std_logic_vector (2 DOWNTO 0);
in_flags : IN nibble; z_out : OUT byte; out_flags : OUT nibble);
END arithmetic_logic_unit;
--
ARCHITECTURE synthesizable_behavioral OF arithmetic_logic_unit IS
BEGIN
coding: PROCESS (a_side, b_side, code, in_flags)
VARIABLE t : std_logic_vector (9 DOWNTO 0);
VARIABLE v, c, z, n : std_logic; --in_flags 3210
BEGIN
CASE code IS
WHEN a_add_b | a_sub_b =>
t := addsub_cv (b_side, a_side, in_flags(2), code(1));
c := t(8); v := t(9); -- other flags are set at the end
WHEN a_and_b =>
t := "00" & ( a_side AND b_side );
c := in_flags(2); v := in_flags(3);
WHEN a_input =>
t := "00" & a_side;
c := in_flags(2); v := in_flags(3);
WHEN b_input =>
t := "00" & b_side;
c := in_flags(2); v := in_flags(3);
WHEN b_compl =>
t := "00" & ( NOT b_side );
c := in_flags(2); v := in_flags(3);
WHEN OTHERS =>
t := "0000000000"; c:= '0'; v := '0';
END CASE;
n := t(7);
z := NOT all_or ( t(7 DOWNTO 0) );
z_out <= t (7 DOWNTO 0);
out_flags <= v & c & z & n;
END PROCESS coding;
END synthesizable_behavioral;