-- Model Name : Synthesizable Dataflow - Parwan Tester
-- Author : Zainalabedin Navabi
-- Last Updated : 09 / 15 / 1996
-- This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
USE EXEMPLAR.exemplar.ALL;
--
LIBRARY parwan_s;
USE parwan_s.ALL;
USE parwan_s.synthesis_parameters.ALL;
USE parwan_s.synthesis_utilities.ALL;
--
ENTITY parwan_tester IS
END parwan_tester;
--
ARCHITECTURE synthesizable OF parwan_tester IS
COMPONENT parwan PORT (clk : IN std_logic; interrupt : IN std_logic;
read_mem, write_mem : OUT std_logic;
databus : INOUT std_logic_vector (7 DOWNTO 0);
adbus : OUT std_logic_vector (11 DOWNTO 0);
halted : OUT std_logic := '0'; ready : IN std_logic := '1'
);
END COMPONENT;
FOR cpu : parwan USE ENTITY parwan_s.par_central_processing_unit(dataflow_synthesizable);
-- FOR cpu : parwan USE ENTITY parwan_s.par_central_processing_unit(behavioral_synthesizable);
COMPONENT memory PORT
(cs, rwbar : IN std_logic;
databus : INOUT byte := "ZZZZZZZZ"; adbus : IN twelve
);
END COMPONENT;
FOR mem : memory USE ENTITY parwan_s.parwan_memory(behavioral);
SIGNAL clock, interrupt, read, write : std_logic := '0';
SIGNAL data : std_logic_vector ( 7 DOWNTO 0 ) := "ZZZZZZZZ";
SIGNAL address : std_logic_vector ( 11 DOWNTO 0 );
SIGNAL cs, halted, ready : std_logic := '0';
CONSTANT duty : TIME := 0.5 US;
CONSTANT period : TIME := duty * 2;
CONSTANT wait_state : INTEGER := 3;
BEGIN
int : interrupt <= '1', '0' AFTER 4500 NS;
clk : clock <= NOT clock AFTER duty WHEN halted = '0' ELSE clock;
cs <= read OR write;
wait_cycle: PROCESS
BEGIN
IF clock = '0' THEN
WAIT FOR 20 NS;
IF cs = '1' THEN
WAIT FOR period * wait_state;
ready <= '1', '0' AFTER period;
END IF;
END IF;
WAIT ON clock;
END PROCESS wait_cycle;
cpu : parwan PORT MAP (clock, interrupt, read, write, data, address, halted, ready);
mem : memory PORT MAP (cs, read, data, address);
END synthesizable;