Application to RTL Design

In order to demonstrate the use of our proposed modeling styles, we have developed an example description for each of the styles discussed on these pages. The example shows how a standart synthesizable RTL description can be transformed into one that simulates faster. We have presented the original synthesizable description of Parwan [ref. Navabi], and the optimized descriptions.

Original Dataflow Synthesizable Parwan	This description has been synthesized by several synthesis tools.
Original Behavioral Synthesizable Parwan	This description simulates faster than dataflow, but uses signals for all registers.
Reduced Data Activity Description for Parwan	This description uses shared variables for all data buses and interconnection lines. Performance of this description is 2-to-3 times better than dataflow description.
Reduced Control Activity Description for Parwan	This description eliminates control control activities and orders calling of data units that operate on data shared variables. Simulation speed is 4-to-5 times faster than synthesizable dataflow description.