HW#1
(3.3) Write a dataflow description for a one-bit comparator. The output of the comparator becomes ‘1’ when its two input bits are equal.
(3.6) Using the style of Figure 3.20, write a behavioral description for a serial subtractor.
(3.9) Modify the description of the def_flop to include a preset input. The flip-flop output must be set to ‘1’ when a synchronous ‘1’ appears on this input.
(3.12) Modify the Description of the Sequence Detector in Figure 3.47 to detect the 1011 sequence. Your circuit should detect overlapping sequences.
HW#2
(4.6) For the architecture description shown below, show the list of all transactions on the signals. Include all initial transactions, final transactions, and those that are discarded. Each transaction should be specified as a parenthesized list of value and time (v, t). Show the resulting waveforms on all the signals. The WAIT UNTIL statement suspends the process until the condition becomes true.
ARCHITECTURE examining OF problem IS
TYPE qit IS ('Z', '1', '0', 'X');
SIGNAL w : qit := '0';
SIGNAL x : qit;
SIGNAL y : qit := 'Z';
SIGNAL z : qit := '1';
SIGNAL a, b : BIT;
BEGIN
a <= '0', '1' AFTER 20 NS;
b <= '0', '1' AFTER 40 NS;
p1: PROCESS
BEGIN
w <= '1' AFTER 8 NS;
w <= '1' AFTER 10 NS;
WAIT UNTIL a = '1';
w <= '0';
y <= TRANSPORT '1' AFTER 5 NS;
WAIT UNTIL b = '1';
w <= '1' AFTER 10 NS;
w <= '0' AFTER 13 NS;
w <= 'Z' AFTER 08 NS;
x <= '1';
y <= TRANSPORT '0' AFTER 12 NS;
y <= TRANSPORT 'Z' AFTER 15 NS;
WAIT;
END PROCESS p1;
z <= x;
END examining;
(4.7) Explain the glitch on signal x in Figure 4.20. Hint: the initial value of all signals are zero.
(4.9) The VHDL code shown below places a two nanosecond positive pulse on a. Assume that toggle_when_transaction returns the complemented value of its first argument when a transaction occurs on its second argument; otherwise, it returns the value of its first argument. Likewise the toggle_when_event function returns the complemented value of its first argument when an event occurs on its second argument; otherwise, it returns the value of its first argument. Considering the assignments in this VHDL code, show all the transactions and events that occur on the t and e signals in a timing diagram.
ARCHITECTURE challenging OF transaction_vs_event IS
SIGNAL a : BIT := '1';
SIGNAL t, e : BIT := '0';
BEGIN
a <= '0', '1' AFTER 10 NS, '0' AFTER 12 NS;
t <= toggle_when_transaction (t, a);
e <= toggle_when_event (e, a);
END challenging;
(4.14) Given the following signal assignments, show all transactions placed on each signal. At each event, show transactions that are appended, overwritten, and are expired. Show resulting waveforms on each signal.
ARCHITECTURE dataflow OF signals IS
TYPE qit IS (‘0’, ‘1’, ‘Z’, ‘X’);
SIGNAL a, b, c : qit := ‘0’;
BEGIN
a <= ‘0’, ‘1’ AFTER 20 NS, ‘Z’ AFTER 30 NS, ‘1’ AFTER 40 NS, ‘0’ AFTER 50 NS;
b <= TRANSPORT ‘0’, a AFTER 14 NS;
c <= ‘1’, a AFTER 10 NS, ‘Z’ AFTER 15 NS, b AFTER 20 NS;
END dataflow;
HW#3
5.1. Write VHDL descriptions for a two-input NOR gate and an XOR gate. Use single delay models similar to the ones used in Section 5.1. Use 4 ns and 7 ns delays for the NOR and XOR respectively. Use inertial delays.
5.5. Write a description of a Full Adder using the gates of Section 5.1 and XOR gate of Problem 5.1. What is the worst case delay for this circuit? The solution to this problem depends on code developed in Problem 5.1.
5.11. Describe an 8-bit adder using the Full Adder description in Problem 5.5. Take advantage of the generate statement. Write a test bench for this adder, and find the worst case delay. The solution to this problem depends on code developed in Problems 5.1 and 5.5.
5.12. If the inputs to the adder in Problem 5.11 are 2's complement numbers, an overflow may occur when adding two positive or two negative numbers. Use this adder in a design of an 8-bit adder with an overflow indication output. Do not modify the description of the original adder; rather, use it in a top level design that instantiates the adder of Problem 5.11 as well as gates of the overflow detection hardware. The solution to this problem depends on code developed in Problems 5.1, 5.5 and 5.11.
5.18. Given the following ENTITY and ARCHITECTURE specifications, write a structural VHDL description for a half-register using a transmission gate and an inverter. A half register has a clock input and a data input and a single output. Write a simple testbench that generates a clock and a data input. Run VHDL simulation to verify the behavior of this construct. Specify the IEEE 1164 std_logic Package option in your VHDL simulation. Use default configuration.
ENTITY transmission IS
PORT (g, s : IN std_logic; d: OUT std_logic);
END;
--
ARCHITECTURE simple OF transmission IS
BEGIN
d <= s AFTER 5 NS WHEN g = ‘1’ ELSE ‘Z’ AFTER 4 NS;
END simple;
ENTITY inverter IS
PORT (a : IN std_logic; z: OUT std_logic);
END;
--
ARCHITECTURE simple OF inverter IS
BEGIN
z <= ‘1’ AFTER 4 NS WHEN a = ‘0’ ELSE ‘0’ AFTER 4 NS;
END simple;
ENTITY half_register IS
PORT (d, c : IN std_logic; qb : OUT std_logic);
END;
Fig. P5.18. CMOS half register
5.19. A master-slave CMOS inverter uses two half-registers each using one phase of a non-overlapping two-phase clock. Use two half-registers to describe a master-slave CMOS flip-flop with the interface shown below. Write a testbench for instantiating the flip-flop, generating two non-overlapping clock phases and test data inputs. Run simulation and verify the operation of this flip-flop. Specifically test for cases that the input changes while the clock is ‘0’. Use default configuration.
ENTITY master_slave_flop IS
PORT (d, c1, c2 : IN std_logic; q : OUT std_logic);
END;
Fig. P5.19. Master-slave CMOS D-type flip-flop