`timescale 1ns/100ps
module counter (reset, clk, counting);
input reset, clk;
output counting;
reg counting;
integer count;
integer limit; initial limit = 8;
always @(negedge clk)
begin
if (reset) count = 0;
else
begin
if (count < limit) count = count + 1;
end
if (count == limit) #8 counting = 0;
else #8 counting = 1;
end
endmodule
`timescale 1ns/100ps
module der_flop (din, reset, enable, clk, qout);
input reset, din, clk, enable;
output qout;
wire dff_in;
reg qout;
always @(negedge clk)
begin
if (reset) qout = #8 1'd0;
else
if (enable)qout = #8 din;
end
endmodule`timescale 1ns/100ps
module der_flop (din, reset, enable, clk, qout);
input reset, din, clk, enable;
output qout;
wire dff_in;
mux2_1 mx (enable, din, qout, dff_in);
flop ff (reset, dff_in, clk, qout);
endmodule
`timescale 1ns/100ps
module fulladder (a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
wire sum = a ^ b ^ cin;
wire cout = (a & b) | (a & cin) | (b & cin);
/*
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
*/
endmodule`timescale 1ns/100ps
module fulladder (a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
assign {sum , cout} = fadd (a, b, cin);
function [1:0] fadd;
input a, b, c;
fadd = {(a ^ b ^ c) , ((a & b) | (a & c) | (b & c))};
endfunction
endmodule
`timescale 1ns/100ps
module flop (reset, din, clk, qout);
input reset, din, clk;
output qout;
reg qout;
always @(negedge clk)
begin
if (reset) qout = #8 1'd0;
else qout = #8 din;
end
endmodule
`timescale 1ns/100ps
module moore_110_detector (x, clk, z);
input x, clk;
output z;
reg [1:0] current;
parameter [1:0] reset = 0, got1 = 1, got11 = 2, got110 = 3;
initial current = reset;
always @(posedge clk)
begin
if (current == reset) current = x ? got1 : reset;
else if (current == got1) current = x ? got11 : reset;
else if (current == got11) current = x ? got11 : got110;
else if (current == got110) current = x ? got1 : reset;
end
assign z = (current == got110) ? 1'b1 : 1'b0;
endmodule
`timescale 1ns/100ps
module mux2_1 (sel, data1, data0, z);
input sel, data1, data0;
output z;
assign #6 z = (sel == 1'b1) ? data1 : data0;
endmodule`timescale 1ns/100ps
module serial_adder (a, b, start, clock, ready, result);
input a, b, start, clock;
output ready;
output [7:0] result;
reg sum, carry, ready, result;
integer count; initial count = 8;
always @(negedge clock)
begin
if (start)
begin
count = 0; carry = 0;
end
else
begin
if (count < 8)
begin
count = count + 1;
sum = a ^ b ^ carry;
carry = (a & b) | (a & carry) | (a & carry);
result = {sum, result [7:1]};
end
end
if (count == 8) ready = 1;
else ready = 0;
end
endmodule
`timescale 1ns/100ps
module serial_adder (a, b, start, clock, ready, result);
input a, b, start, clock;
output ready;
output [7:0] result;
wire serial_sum, carry_in, carry_out, counting;
fulladder u1 (a, b, carry_in, serial_sum, carry_out);
flop u2 (start, carry_out, clock, carry_in);
counter u3 (start, clock, counting);
shifter u4 (serial_sum, start, counting, clock, result);
assign ready = ~ counting;
endmodule`timescale 1ns/100ps
module serial_adder (a, b, start, clock, ready, result);
input a, b, start, clock;
output ready;
output [7:0] result;
reg sum, carry, ready, result;
reg [3:0] count; initial count = 4'b1000;
always @(negedge clock)
begin
if (start)
begin
count = 0; carry = 0;
end
else
begin
if (count < 8)
begin
count = count + 1;
sum = a ^ b ^ carry;
carry = (a & b) | (a & carry) | (a & carry);
result = {sum, result [7:1]};
end
end
if (count == 8) ready = 1;
else ready = 0;
end
endmodule
`timescale 1ns/100ps
module shifter (sin, reset, enable, clk, parout);
input sin, reset, enable, clk;
output [7:0] parout;
reg [7:0] parout;
always @(negedge clk)
parout = (reset) ? 8'd0 : ((enable) ? {sin, parout [7:1]} : parout);
endmodule
//Verilog test bench and stimulus for falling edge D flip-flop
`timescale 10ns/1ns
module test_shifter;
reg sin, reset, enable, clk;
wire [7:0] parout;
shifter u1(sin, reset, enable, clk, parout);
initial
begin
clk = 1'b1;
sin = 1'b0;
reset = 1'b1;
enable = 1'b0;
#05 reset = 1'b1; #11 reset = 1'b0;
#12 enable = 1'b1;
#54 $finish;
end
always #3.1 sin = ~ sin;
always #2 clk = ~ clk;
endmodule
`timescale 1ns/100ps
module shifter (sin, reset, enable, clk, parout);
input sin, reset, enable, clk;
output [7:0] parout;
der_flop b7 ( sin, reset, enable, clk, parout[7]);
der_flop b6 (parout[7], reset, enable, clk, parout[6]);
der_flop b5 (parout[6], reset, enable, clk, parout[5]);
der_flop b4 (parout[5], reset, enable, clk, parout[4]);
der_flop b3 (parout[4], reset, enable, clk, parout[3]);
der_flop b2 (parout[3], reset, enable, clk, parout[2]);
der_flop b1 (parout[2], reset, enable, clk, parout[1]);
der_flop b0 (parout[1], reset, enable, clk, parout[0]);
endmodule