Project Supervisor: Dr. Zainalabedin Navabi

Engineer Researchers: Fatemeh Khaani Alireza Khalafi Armita Peymandoust Massoud Shadfar

1. Adapting Differential Fault Simulation For VHDL Implementation :
   To reduce simulation events, a differential fault simulator simulates all faulty circuits for the same test input before applying the next test vector to the circuit. Activities occur in limited parts of a gate level circuit between application of faults for the same input vector. Adapting this fault simulation technique to the programming environment of VHDL and its use in fault simulation of sequential circuits will be presented in this paper. Modeling gate level lines and components in VHDL will be presented.
   
   
2. New VHDL Based Critical Path Tracing Method for Fault Simulation :
   This paper presents a new method of critical path tracing for fault simulation. The details of the method, called one-pass critical path tracing, and its implementation in VHDL will be presented here. One-pass CPT is achieved by use of VHDL models for basic logical gates. By communicating via their ports, gate models a netlist will report faults that are detected on their ports due to application of test vectors at their primary inputs.
   
   
3. Using VHDL Critical Path Tracing Models for Pseudo Random Test Generation :
   VHDL gate level models for fault simulation by the Critical Path Tracing method have been developed. These models will be used by a VHDL test bench for pseudo random test generation. Modeling strategy and the test environment will be described in this paper.
   
   
4. Implementing Adaptive Random Test Generation in VHDL :
   This paper presents a VHDL test bench for random generation of test vectors for gate level structural digital circuits. Adaptive generation of test vectors is being focused here. In this approach, one of several predetermined vector generation schemes is selected based on the anticipated fault detection rate.
   
   
5. VHDL Structural Models for the Implementation of Path Sensitization Test Generation :
   We have developed a modeling strategy in VHDL for gate level components for automatic test generation. A gate level structural description using these models is capable of generating its own test vectors for induced faults on its lines. A testbench places a fault on a line of the gate level description, and the models communicate through their ports for finding a test vector detecting the fault. This paper describes a test environment, our VHDL models, and a fault activation testbench.
   
   
6. HDL Modeling for Equivalence Fault Collapsing :
   In the area of digital system test, fault collapsing is referred to the process of reducing faults in a circuit to only those that can be distinguished. In local fault collapsing, one fault is selected from each of the equivalent fault classes of logical gates. The selection will be based on the connections made to the ports of a gate. We have developed VHDL gate models for local equivalent fault collapsing. This paper presents test environments using fault collapsing, our VHDL modeling strategies, and an example.
   
   
7. BIST (Built in self test) Modeling and Its Application in Design Verification :
   Built in self test (BIST) has been used for testability of digital systems. VHDL modeling of BIST, not only can evaluate circuit under design for its testability, it can also be used for top-down design verification. This paper describes a VHDL modeling strategy for register level description of BIST. We will show how a BIST architecture inserted into a top level design can become useful in the lower level implementation of upper level components of a design. The paper will show application of the technique develop to a simple RISC architecture.
   
   

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Last modified October 07, 1996. Funda Kutay is in charge of this page, funda@ece.neu.edu, Under provision of: Dr. Zain Navabi, navabi@ece.neu.edu