VHDL Model of the 8051 Microcontroller

If you are interested in VHDL and the 8051, you have come to the correct spot. For general infomation try the following:
General 8051 & Keil Compiler Links

Behavioral Model
Structural Model - in a quazi synthesizable coding style

NOTE: The following represents an undergraduate research project, and therefore has no warranty or guarantee to actually work. This project MAY NOT be used for profit without the express permssion of the author (Michael Mayer or Dr. Hardy J. Pottinger).

In fact, I can guarantee that there are many more bugs that have not yet been found, but this is a good start towards a behavioral 8051 model.

Please send any comments / questions / job offers, er I mean, bug reports to mrmayer@computer.org.
Thank you,
Michael Mayer

Digital System Modeling Students!
If you are enrolled in EE 301, here is more information for you.

VHDL Behavioral Model

Created during the fall semester of 1997 based on the Intel 8051 Microcontroller.

Features

Limitations

The following files can be downloaded from the 8051 behav src directory.

build             -- script to build the components of system
latch373.vhd      -- 8 D-LATCHES
max232.vhd        -- Nothing yet
mc8051.vhd        -- The model of the 8051 MicroController
  (requires uart.vhd)
nvsram.vhd        -- SRAM that will only read from hex files
pack8051.vhd      -- Supporting package for mc8051.vhd
quickhdl.ini      -- Link to ini file
system.vhd        -- Toplevel VHDL Structural model of a system containing 
                  -- 8051, ram, 373 latches, and clock process.
tb.vhd            -- Old Testbench of mc8051.vhd using pwmodulator 

Miscellaneous Hex Format 8051 programs. Note, at the moment, the tb.vhd file above points to code.hex. This should be the pwmdcd.hex file.

VHDL Structural Model

Created during the winter semester of 1998, this model more closely resembles a synthesiable type structure. IN PROGRESS The following model is still being written, so what you find here is likely to change daily, even hourly, and is NOT EVEN GUARANTEED TO COMPILE!!!
The goal is to eventually have a structural version of an 8051 core which could later be optimized for a synthesis package.

Renoir - by Mentor Graphics - is being used for the structural architectures. This application makes it much easier to handle multiple versions of architectures, do net-listing, and maintain entities. If you have any questions about this package, let me know.

Links:
Top-Level Structure Gif - large picture
CPU Core Structure Gif
Another Structural component - the Program control
Structural Source Files