--
-- Rcsid[] = "$Id: hl_de_wz.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

--  This logic contains the HL, DE and WZ register pairs
--  and their respective write enable and output enable logic.
--  NOTE : There is a separate path from DE pair to HL pair
--         input for the XCHG instruction.


entity hl_de_wz is
port(B16BO: out bit_vector(0 to 15);
     B8BO:  out bit_vector(0 to 7);
     D: in bit_vector(0 to 15);
     WRH,WRL,WRHL,WRD,WRE,WRDE,HOUT,LOUT,HLOUT,DOUT,EOUT,DEOUT,CLK,
     ID19,ID3,ID13,WRZ,WRW,WZOUT,WRWZ,T4,GND,VCC: in bit);
end;

architecture structure of hl_de_wz is

component regpairs
port(Q: out bit_vector(0 to 15);
     D: in  bit_vector(0 to 15);
     CLEAR,VCC,WRLOW,WRHIGH,WRBOTH,CK: in bit);
end component;

component mux_4bit
port(Y: out bit_vector(0 to 3);
     A,B: in bit_vector(0 to 3);
     choose: in bit);
end component;

component ocnand
port(O: out bit_vector(7 downto 0);
     I: in bit_vector(7 downto 0);
     ENABLE: in bit);
end component;

signal qh: bit_vector(0 to 15);
signal qd: bit_vector(0 to 15);
signal qw: bit_vector(0 to 15);
signal m, w: bit_vector(0 to 15);
signal CLKBAR, xchg: bit;

begin
HL_PAIR : REGPAIRS port map(qh(0 to 15), m(0 to 15),VCC,VCC,WRL,WRH,WRHL,CLK);
DE_PAIR : REGPAIRS port map(qd(0 to 15), D(0 to 15),VCC,VCC,WRE,WRD,WRDE,CLK);
WZ_PAIR : REGPAIRS port map(qw(0 to 15), w(0 to 15),VCC,VCC,WRZ,WRW,WRWZ,CLKBAR);

U2 : mux_4bit port map(m(0 to 3),   D(0 to 3),   qd(0 to 3),   xchg);
U3 : mux_4bit port map(m(4 to 7),   D(4 to 7),   qd(4 to 7),   xchg);
U4 : mux_4bit port map(m(8 to 11),  D(8 to 11),  qd(8 to 11),  xchg);
U5 : mux_4bit port map(m(12 to 15), D(12 to 15), qd(12 to 15), xchg);

U6 :  OCNAND port map(B16BO(0 to 7), qh(0 to 7), HLOUT);
U7 :  OCNAND port map(B16BO(8 to 15),qh(8 to 15),HLOUT);
U10 : OCNAND port map(B8BO(0 to 7),  qh(0 to 7), LOUT);
U11 : OCNAND port map(B8BO(0 to 7),  qh(8 to 15),HOUT);

U8 :  OCNAND port map(B16BO(0 to 7), qd(0 to 7), DEOUT);
U9 :  OCNAND port map(B16BO(8 to 15),qd(8 to 15),DEOUT);
U12 : OCNAND port map(B8BO(0 to 7),  qd(0 to 7), EOUT);
U13 : OCNAND port map(B8BO(0 to 7),  qd(8 to 15),DOUT);

U14 : OCNAND port map(B16BO(0 to 7), qw(0 to 7),WZOUT);
U15 : OCNAND port map(B16BO(8 to 15),qw(8 to 15),WZOUT);

U16 : inv_gate generic map(1,1) port map(CLKBAR,CLK);
U17 : nor_gate generic map(1,1) port map(xchg,T4,ID19,ID3,ID13);

U18 : mux_4bit port map(w(0 to 3),   D(0 to 3),   qh(0 to 3),   xchg);
U19 : mux_4bit port map(w(4 to 7),   D(4 to 7),   qh(4 to 7),   xchg);
U20 : mux_4bit port map(w(8 to 11),  D(8 to 11),  qh(8 to 11),  xchg);
U21 : mux_4bit port map(w(12 to 15), D(12 to 15), qh(12 to 15), xchg);
end structure;

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