-- +-----------------------------+ -- | Library: image_processing | -- | designer : Tim Pagden | -- | opened: 07 Jul 1996 | -- +-----------------------------+ library vfp; architecture RTL of ipcra_generic is -- just because an architecture is called RTL doesn't mean it's synthesisable! use vfp.bus_class.all; -- 16; 3,3 constant chain_base : integer := ((image_width * (window.depth - 1)) + window.width) / 2; -- 17 constant chain_extra : integer := ((image_width * (window.depth - 1)) + window.width) mod 2; -- 1 constant chain_length : integer := chain_base + chain_extra; -- 18 signal pos_chain : ulogic_8_vector(0 to chain_length-1); -- 0 to 17 signal neg_chain : ulogic_8_vector(0 to chain_length-1); -- 0 to 17 begin chain_pos : process (clock) begin if clock'event and clock='1' then pos_chain(0) <= pixel_in; for i in 1 to chain_length-1 loop pos_chain(i) <= pos_chain(i-1); end loop; end if; end process; chain_neg : process (clock) begin if clock'event and clock='0' then neg_chain(0) <= pixel_in; for i in 1 to chain_length-1 loop neg_chain(i) <= neg_chain(i-1); end loop; end if; end process; window_depth: for j in 0 to window.depth-1 generate window_width: for i in 0 to window.width-1 generate -- generate declarative part, '93 only constant cells_per_edge : integer := (image_width / 2); -- 8 -- generate statement part select_pos_neg : process (clock, neg_chain((cells_per_edge * j) + i/2), pos_chain((cells_per_edge * j) + i/2)) begin if (i mod 2) = 0 then if clock = '0' then window_pixel((j * window.width) + i) <= neg_chain((cells_per_edge * j) + i/2); else window_pixel((j * window.width) + i) <= pos_chain((cells_per_edge * j) + i/2); end if; else if clock = '0' then window_pixel((j * window.width) + i) <= pos_chain((cells_per_edge * j) + i/2); else window_pixel((j * window.width) + i) <= neg_chain((cells_per_edge * j) + i/2); end if; end if; end process; end generate; end generate; end RTL;