read DIG_CAM_GATE2.db set_operating_conditions -library "lsi_10k" "WCCOM" set_wire_load "10x10" -library "lsi_10k" set_driving_cell -cell AN2P -library lsi_10k all_inputs() create_clock find(port, "clk") -period 5 set_load 1000 find(net, "*", -hierarchy) set_load 312000 find(net, "addr*"); set_load 312000 find(net, "rd"); set_load 312000 find(net, "wr"); set_load 312000 find(net, "data*") set_load 312000 find(net, "rdy"); set_load 312000 find(net, "paddr*"); set_load 312000 find(net, "pdata*"); set_load 312000 find(net, "ior"); set_load 312000 find(net, "iow"); set_load 312000 find(net, "ale"); set_load 312000 find(net, "iochrdy"); include dig_cam_sa2.scr check_design report_power -cumulative -net -analysis_effort high report_power -analysis_effort high exit <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>