---
-- Dalton Project
-- Tony Givargis, Rilesh Patel, Deepa Varghese, Roman Lysecky
-- 12/31/98
-- Version 1.2
-- Notes: This file implements the Digital Camera, a.k.a., DIG_CAM, device.
-- So far, DIG_CAM consists of a memory module, bios module, and...
--
--*************************************************************************--
library lsi_10k;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use lsi_10k.all;
--*************************************************************************--
entity DIG_CAM is
port( scan_clk : in STD_LOGIC;
scan_data : in UNSIGNED(7 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC );
end DIG_CAM;
--*************************************************************************--
architecture BHV_DIG_CAM of DIG_CAM is
--
-- component declarations
--
component MIPS
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
cs : in STD_LOGIC;
data : inout UNSIGNED(31 downto 0);
addr : out UNSIGNED(22 downto 0);
rd : out STD_LOGIC;
wr : out STD_LOGIC;
rdy : in STD_LOGIC;
adr : out UNSIGNED(31 downto 0) );
end component;
component BIOS
generic( COMP_RATIO : INTEGER := 1 );
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
data : out UNSIGNED(31 downto 0);
addr : out UNSIGNED(22 downto 0);
rd : out STD_LOGIC;
wr : out STD_LOGIC;
rdy : in STD_LOGIC;
cs : out STD_LOGIC );
end component;
component MEMORY
generic( MAX_MEM_SIZE : INTEGER := 350 );
port( clk : in STD_LOGIC;
rst : STD_LOGIC;
data : inout UNSIGNED(31 downto 0);
addr : in UNSIGNED(22 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC);
end component;
component BRIDGE
generic(START_ADDR : INTEGER := 512);
port( rst : in STD_LOGIC;
clk : in STD_LOGIC;
data : inout UNSIGNED(31 downto 0);
addr : in UNSIGNED(22 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC;
rdy : out STD_LOGIC;
pdata : inout UNSIGNED(31 downto 0);
paddr : out UNSIGNED(22 downto 0);
ior : out STD_LOGIC;
iow : out STD_LOGIC;
ale : out STD_LOGIC;
iochrdy : in STD_LOGIC);
end component;
component CODEC
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027;
COMPRESSION : INTEGER:=1);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
pdata : inout UNSIGNED(31 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC );
end component;
component CCD
generic( IMAGE_READY_REG : INTEGER := 512;
IMAGE_START_REG : INTEGER := 513;
DATA_REG : INTEGER := 514;
IMAGE_WIDTH : INTEGER range 1 to 1024 := 16;
IMAGE_HEIGHT : INTEGER range 1 to 1024 := 16);
port( scan_clk : in STD_LOGIC;
scan_data : in UNSIGNED(7 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
pdata : inout UNSIGNED(31 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC );
end component;
component PPP
generic( A_PORT_ADDR : INTEGER:=1028;
B_PORT_ADDR : INTEGER:=1029;
C_PORT_ADDR : INTEGER:=1030;
CONT_REG_ADDR : INTEGER:=1031);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
pdata : inout UNSIGNED(31 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC;
paen : out STD_LOGIC;
pben : out STD_LOGIC;
pcen : out UNSIGNED(7 downto 0);
pai : in UNSIGNED(7 downto 0);
pbi : in UNSIGNED(7 downto 0);
pci : in UNSIGNED(7 downto 0);
pao : out UNSIGNED(7 downto 0);
pbo : out UNSIGNED(7 downto 0);
pco : out UNSIGNED(7 downto 0));
end component;
component PC16550
generic(INPUT_ADDR : INTEGER := 3000);
port(clk : in STD_LOGIC;
rst : in STD_LOGIC;
pdata : inout UNSIGNED (31 downto 0);
paddr : in UNSIGNED (22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC;
sout : out STD_LOGIC );
end component;
--
-- define signals for the bus
--
signal data : UNSIGNED(31 downto 0);
signal addr : UNSIGNED(22 downto 0);
signal rd, wr, rdy : STD_LOGIC;
signal bios_done : STD_LOGIC;
signal adr : UNSIGNED(31 downto 0);
signal pdata : UNSIGNED(31 downto 0);
signal paddr : UNSIGNED(22 downto 0);
signal ior, iow, ale, iochrdy : STD_LOGIC;
signal sout : STD_LOGIC;
signal paen, pben : STD_LOGIC;
signal pcen, pao, pbo, pco, pai, pbi, pci: UNSIGNED(7 downto 0);
begin
--
-- instantiate the BIOS and MEMORY devices
--
MIPS_1: MIPS port map(clk, rst, bios_done, data, addr, rd, wr, rdy,
adr);
BIOS_1: BIOS generic map (COMP_RATIO => 4)
port map(clk, rst, data, addr, rd, wr, rdy, bios_done);
MEMORY_1: MEMORY port map(clk, rst, data, addr, rd, wr);
BRIDGE_1: BRIDGE port map(rst, clk, data, addr, rd, wr, rdy,
pdata, paddr, ior, iow, ale, iochrdy);
CODEC_1: CODEC generic map (COMPRESSION => 4)
port map(clk, rst, pdata, paddr, ior, iow, ale,
iochrdy);
CCD_1: CCD port map(scan_clk, scan_data, clk, rst, pdata, paddr,
ior, iow, ale, iochrdy);
PC16550_1: PC16550
port map(clk, rst, pdata, paddr, ior, iow, ale,
iochrdy, sout);
PPP_1: PPP
port map(clk, rst, pdata, paddr,ior, iow, ale,
iochrdy, paen, pben, pcen, pai, pbi, pci,
pao, pbo, pco);
end BHV_DIG_CAM;
--*************************************************************************--
--configuration CFG_DIG_CAM of DIG_CAM is
-- for BHV_DIG_CAM
-- for MIPS_1 : MIPS use configuration WORK.CFG_MIPS;
-- end for;
-- for BIOS_1 : BIOS use configuration WORK.CFG_BIOS;
-- end for;
-- for MEMORY_1 : MEMORY use configuration WORK.CFG_MEMORY;
-- end for;
-- for BRIDGE_1 : BRIDGE use configuration WORK.CFG_BRIDGE;
-- end for;
-- for CODEC_1 : CODEC use configuration WORK.CFG_CODEC;
-- end for;
-- for CCD_1 : CCD use configuration WORK.CFG_CCD;
-- end for;
-- for PPP_1 : PPP use configuration WORK.CFG_PPP;
-- end for;
-- for PC16550_1 : PC16550 use configuration WORK.CFG_PC16550;
-- end for;
-- end for ;
--end CFG_DIG_CAM;
-- end of file --
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