analyze -format vhdl -lib WORK {"PC16550.vhd"} elaborate CFG_PC16550 -lib DEFAULT -update include compile.scr vhdlout_top_configuration_name = "CFG_PC16550_SYN" vhdlout_top_configuration_entity_name = "PC16550" write -format db -hierarchy -output "PC16550_GATE.db" write -format vhdl -hierarchy -output "PC16550_GATE.vhd" report_area exit <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>