--
-- Dalton Project
-- Tony Givargis, Rilesh Patel, Deepa Varghese, Roman Lysecky
-- 07/14/98
-- Version 1.0
-- Notes: This file implements the CODEC device. This device compress
-- or decompress the data
--
-- The CODEC has three 32 bit registers: the input register to put
-- the data that to be compress or decompress, the output register
-- that stores the compressed or decompressed data, and control/
-- status registers.
--
-- IN_REG:
--
-- MSB LSB
-- ---------------------------------------------------------------
-- | NU .......................................... NU | B/W |
-- ---------------------------------------------------------------
-- 8-bits
-- OUT_REG:
--
-- MSB LSB
-- ---------------------------------------------------------------
-- | NU .......................................... NU | B/W |
-- ---------------------------------------------------------------
-- 8-bits
--
-- STAT_REG:
--
-- MSB LSB
-- ---------------------------------------------------------------
-- |NU................................................... NU|READY |
-- ---------------------------------------------------------------
-- ^
-- |
-- |
-- |
-- set = data is ready----------------------------------------
--
--
--
-- CONT_REG:
--
-- MSB LSB
-- ---------------------------------------------------------------
-- |NU...........................................NU|COMPRESS |START|
-- ---------------------------------------------------------------
-- ^ ^
-- | |
-- | |
-- set to compress and reset to decompress ------------ |
-- set to start the operation --------------------------------
--
--*************************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--*************************************************************************--
entity CODEC_IN is
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027;
COMPRESSION : INTEGER := 4);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ib_data : inout UNSIGNED(31 downto 0);
ib_addr : in UNSIGNED(22 downto 0);
ib_wr : in STD_LOGIC;
ib_rd : in STD_LOGIC;
ib_valid : out STD_LOGIC );
end CODEC_IN;
--*************************************************************************--
architecture BHV_CODEC_IN of CODEC_IN is
--
-- type declarations
--
type STATE_TYPE is (IDLE,COMP,DECOMP,DONE);
--
-- constant declarations
--
constant Z_32 : UNSIGNED(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
constant Z_23 : UNSIGNED(22 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZ";
constant C0_32 : UNSIGNED(31 downto 0) :=
"00000000000000000000000000000000";
constant C1_32 : UNSIGNED(31 downto 0) :=
"00000000000000000000000000000001";
--
-- type declarations
--
subtype REG_CELL is UNSIGNED(31 downto 0);
type REG_TYPE is array(COMPRESSION-1 downto 0) of REG_CELL;
--
-- signal declarations
--
signal location: INTEGER range 0 to 4;
signal in_reg : REG_TYPE;
signal out_reg,stat_reg,cont_reg: UNSIGNED(31 downto 0);
signal state : STATE_TYPE;
begin
process(clk, rst)
variable temp, temp2 : INTEGER range 0 to 31;
begin
if( rst = '1' ) then
stat_reg <= C0_32;
out_reg <= C0_32;
state <= IDLE;
elsif( clk'event and clk = '1' ) then
case(state) is
when IDLE =>
if(cont_reg(0)='1' ) then
stat_reg(0) <= '0';
if( cont_reg(1) = '1' ) then
state <= COMP;
else
state <= DECOMP;
end if;
end if;
when COMP =>
for temp in 0 to COMPRESSION-1 loop
temp2 := temp * 8;
out_reg(temp2+7 downto temp2) <= in_reg(temp)(7 downto 0);
end loop;
state <= DONE;
when DECOMP =>
out_reg <= C0_32;
for temp in 0 to COMPRESSION-1 loop
temp2 := temp * 8;
out_reg(temp2+7 downto temp2) <= in_reg(temp)(7 downto 0);
end loop;
state <= DONE;
when DONE =>
stat_reg(0) <= '1';
if( cont_reg(0) = '0' ) then
state <= IDLE;
end if;
end case;
end if;
end process;
--
-- register read/write process
--
process(clk, rst)
begin
if( rst = '1' ) then
--
-- steady state
--
ib_data <= Z_32;
ib_valid <= '0';
cont_reg <= C0_32;
location <= 0;
for i in 0 to (COMPRESSION-1) loop
in_reg(i) <= C0_32;
end loop; -- i
elsif( clk'event and clk = '1' ) then
--
-- steady state
--
ib_data <= Z_32;
ib_valid <= '0';
if( ib_wr = '1' ) then
if( ib_addr =
conv_integer(CONT_REG_ADDR) ) then
cont_reg <= ib_data ;
elsif( ib_addr =
conv_integer(IN_REG_ADDR) ) then
in_reg(location) <= ib_data;
location <= location + 1;
if(location = COMPRESSION-1) then
location <= 0;
end if;
end if;
elsif( ib_rd = '1' ) then
if( ib_addr =
conv_integer(STAT_REG_ADDR) ) then
ib_data <= stat_reg;
ib_valid <= '1';
elsif(ib_addr =
conv_integer(OUT_REG_ADDR)) then
ib_data <= out_reg;
ib_valid <= '1';
end if;
end if;
end if;
end process;
end BHV_CODEC_IN;
--*************************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--*************************************************************************--
entity CODEC_IM is
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ib_data : inout UNSIGNED(31 downto 0);
ib_addr : out UNSIGNED(22 downto 0);
ib_wr : out STD_LOGIC;
ib_rd : out STD_LOGIC;
ib_valid : in STD_LOGIC;
pdata : inout UNSIGNED(31 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC );
end CODEC_IM;
--*************************************************************************--
architecture BHV_CODEC_IM of CODEC_IM is
--
-- type declarations
--
type STATE_TYPE is (IDLE_S, READ_WRITE, READ1_S, READ2_S, WRITE_S );
--
-- constant declarations
--
constant Z_32 : UNSIGNED(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
constant Z_23 : UNSIGNED(22 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZ";
constant C0_32 : UNSIGNED(31 downto 0) :=
"00000000000000000000000000000000";
constant C0_23 : UNSIGNED(22 downto 0) :=
"00000000000000000000000";
--
-- signal declarations
--
signal state : STATE_TYPE;
begin
process(clk, rst)
begin
if ( rst = '1' ) then
--
-- steady state
--
state <= IDLE_S;
pdata <= Z_32;
iochrdy <= 'Z';
ib_data <= Z_32;
ib_addr <= C0_23;
ib_rd <= '0';
ib_wr <= '0';
elsif ( clk'event and clk = '1' ) then
--
-- steady state
--
pdata <= Z_32;
iochrdy <= 'Z';
ib_data <= Z_32;
ib_addr <= C0_23;
ib_rd <= '0';
ib_wr <= '0';
--
-- otherwise
--
case( state ) is
when IDLE_S =>
if(ale = '1') then
if ( paddr = conv_integer(STAT_REG_ADDR) or
paddr = conv_integer(CONT_REG_ADDR) or
paddr = conv_integer(IN_REG_ADDR) or
paddr = conv_integer(OUT_REG_ADDR) ) then
state <= READ_WRITE;
iochrdy <= '0';
else
state <= IDLE_S;
end if;
else
state <= IDLE_S;
end if;
when READ_WRITE =>
if( ior = '1' ) then
iochrdy <= '0';
ib_addr <= paddr;
ib_rd <= '1';
state <= READ1_S;
elsif( iow = '1' ) then
iochrdy <= '0';
ib_data <= pdata;
ib_addr <= paddr;
ib_wr <= '1';
state <= WRITE_S;
else
state <= IDLE_S;
end if;
when READ1_S =>
iochrdy <= '0';
state <= READ2_S;
when READ2_S =>
if( ib_valid = '1' ) then
pdata <= ib_data;
iochrdy <= '1';
state <= IDLE_S;
else
iochrdy <= '0';
state <= READ2_S;
end if;
when WRITE_S =>
if(iow = '1') then
iochrdy <= '1';
state <= WRITE_S;
else
state <= IDLE_S;
end if;
when others =>
state <= IDLE_S;
end case;
end if;
end process;
end BHV_CODEC_IM;
--*************************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--*************************************************************************--
entity CODEC is
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027;
COMPRESSION : INTEGER:=4);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
pdata : inout UNSIGNED(31 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC );
end CODEC;
--*************************************************************************--
architecture STR_CODEC of CODEC is
--
-- component declarations
--
component CODEC_IN
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027;
COMPRESSION : INTEGER:=4);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ib_data : inout UNSIGNED(31 downto 0);
ib_addr : in UNSIGNED(22 downto 0);
ib_wr : in STD_LOGIC;
ib_rd : in STD_LOGIC;
ib_valid : out STD_LOGIC );
end component;
component CODEC_IM
generic( IN_REG_ADDR : INTEGER:=1024;
OUT_REG_ADDR : INTEGER:=1025;
STAT_REG_ADDR : INTEGER:=1026;
CONT_REG_ADDR : INTEGER:=1027);
port( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ib_data : inout UNSIGNED(31 downto 0);
ib_addr : out UNSIGNED(22 downto 0);
ib_wr : out STD_LOGIC;
ib_rd : out STD_LOGIC;
ib_valid : in STD_LOGIC;
pdata : inout UNSIGNED(31 downto 0);
paddr : in UNSIGNED(22 downto 0);
ior : in STD_LOGIC;
iow : in STD_LOGIC;
ale : in STD_LOGIC;
iochrdy : out STD_LOGIC );
end component;
--
-- component configurations
--
for all : CODEC_IN use entity WORK.CODEC_IN(BHV_CODEC_IN);
for all : CODEC_IM use entity WORK.CODEC_IM(BHV_CODEC_IM);
--
-- signals
--
signal ib_data : UNSIGNED(31 downto 0);
signal ib_addr : UNSIGNED(22 downto 0);
signal ib_wr, ib_rd, ib_valid : STD_LOGIC;
begin
--
-- component instantiations
--
U1 : CODEC_IN
generic map(IN_REG_ADDR,OUT_REG_ADDR,
STAT_REG_ADDR,CONT_REG_ADDR,COMPRESSION)
port map(clk, rst, ib_data, ib_addr, ib_wr, ib_rd, ib_valid);
U2 : CODEC_IM
generic map(IN_REG_ADDR,OUT_REG_ADDR,
STAT_REG_ADDR,CONT_REG_ADDR)
port map(clk, rst, ib_data, ib_addr, ib_wr,
ib_rd, ib_valid, pdata, paddr, ior, iow, ale, iochrdy);
end STR_CODEC;
--*************************************************************************--
-- end of file --
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