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FPGA-8051 General Description
Available in both Verilog netlist and RTL source form,
QuickCores FPGA-8051 is 100% object code
compatible with the industry standard 8051. But there
are some significant architectural differences which lend
QuickCores FPGA-8051 design to implementation in
FPGAs. These architectural differences include a three-stage instruction pipeline, single-clock design, and
inherent real-time monitor and debugging capability.
Single Clock, Three-Stage Pipeline Design
QuickCores FPGA-8051 architecture is based on a
single-clock, three-stage instruction pipeline design.
This means that unlike the industry standard 8051 where
it takes at lease 12 clocks to execute a single-byte
instruction, the QuickCores FPGA-8051 can do it in one
clock.
Real-Time Monitor and Debug Architecture
QuickCores FPGA-8051 architecture is adapted to
include a built-in real-time monitoring a debug capability.
The real-time monitor architecture gives the user the
ability to examine and edit the 8051's memory and
registers on-the-fly and without any software overhead on
the target side (since it's all done in hardware).
Communication with the core's on-chip debug logic is
typically by way of a JTAG connection. Real-time
monitoring and debug functions that are supported
include: download, examine, edit program/data memory
and registers, h/w and s/w breakpoints, single-steps
(including real-time single-steps while other processes
continue), real-time trace buffer with time-stamp, four-level event sequencing/triggering, event counters, and
on/off trace control.
User-Defineable SFR Block
To enable easy customization, the 8051 Special
Function Register (SFR) block is partitioned into the
CPU SFR block and the User SFR block with the later
being instantiated at the top level of the design. All the
required CPU hooks are provided in the User SFR
module ports. Included in the FPGA-8051 netlist library
are the dual 16-bit counter/timer module, interrupt
controller, 8-bit parallel port, standard serial port, and
DAC7512 serial port. Example User SFR modules
written in Verilog are provided in the netlist library and
serve as a guide for customizing your own 8051 microcontroller
Download FPGA-8051 CORES
This Verilog netlist is
generic in that they can be synthesized with virtually any Verilog synthesis
tool including Synplicity, Synopsys and ALTERA's free Quartus II Web
Edition software. This core have been implemented successfully in Actel
ProASICPLUS, ALTERA Cyclone and
QuickLogic Eclipse II FPGAs. This core have a built-in, JTAG real-time
monitoring and debug capability which is enabled when the "debug.v" module
is instantiated in the top level design
 파일명: Q8051.zip (34,513 bytes) 
Download Brief Sheet of FPGA-8051 Soft Core Real-Time Development Kit
For Actel ProASICPLUS 파일명: ProASIC_8051_brief.pdf (572,856 bytes)
For ALTERA Cyclone 파일명: cyclone144.pdf (801,511 bytes)
TEKNOTES
Configuring Keil Software uVision2 IDE to work with QuickCores FPGA-embeddable 8051 microcontrollers.
파일명: Keil_QC_BV.pdf (392,527 bytes)
파일명: keilqc8051.exe (6,459,232 bytes)
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