The HC11 CPU Core is a fully-synthesizable VHDL implementation of the HC11 CPU. All instructions are currently implemented with the exception of the divide instructions. The GM HC11 CPU Core package includes the synthesizable core, projects, self-checking testbenches and a debugger.
We have synthesised the CPU core for both Xilinx and Altera FPGAs using FPGA Express from Synopsys. The design used 1076 slices and runs at 31MHz on the Xilinx Virtex 400E part. On the Altera APEX 20K100 part, the design ran at 32MHz and used 2142 LEs.
The GM HC11 CPU Core package is a free download. You can also redistribute synthesized designs based on this package for commercial or non-commercial use. However, you may not distribute the package any further in source form. For more information, see the license.txt file included in the package.
You may download it now.
The project files and debugger require VHDL Studio, which may be downloaded here.