entity fg_20_16 is end entity fg_20_16; architecture test of fg_20_16 is signal clk : bit; attribute synthesis_hint : string; begin -- code from book controller : process is attribute synthesis_hint of control_loop : label is "implementation:FSM(clk)"; -- . . . begin -- . . . -- initialization control_loop : loop wait until clk = '1'; -- . . . end loop; end process controller; -- end code fom book end architecture test; <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>