--
-- Component : main_control
--
-- Generated by System Architect version v8.4_3.7 by mrmayer on Feb 9, 1997
--
-- clock :: sys_clk rising
-- reset :: sys_rst active_low asynchronous_reset
--

ARCHITECTURE state_machine OF main_control IS
   TYPE main_control_state_type is (
      cleared,
      timing,
      paused,
      frozen_timing,
      frozen_paused
   );


   -- SDS Defined State Signals
   SIGNAL current_state : main_control_state_type := cleared ;
   SIGNAL next_state : main_control_state_type := cleared ;
BEGIN

   -------------------------------------------------------------------
   clocked : PROCESS (
      current_time,
      paused_time,
      set_reset,
      start_stop,
      sys_clk,
      sys_rst
   )
   -------------------------------------------------------------------
   BEGIN
      IF ( sys_rst = '0' ) THEN
         current_state <= cleared;
      ELSIF ( sys_clk'EVENT AND sys_clk = '1' AND sys_clk'LAST_VALUE = '0' ) THEN
         current_state <= next_state;
      END IF;

   END PROCESS clocked ;

   -------------------------------------------------------------------
   set_next_state : PROCESS (
      current_state,
      current_time,
      paused_time,
      set_reset,
      start_stop,
      sys_clk,
      sys_rst
   )
   -------------------------------------------------------------------
   BEGIN
      next_state <= current_state;
      CASE current_state IS
      WHEN cleared =>
         IF ( start_stop='1' ) THEN
            next_state <= timing;
         END IF;

      WHEN timing =>
         IF ( start_stop='1' ) THEN
            next_state <= paused;
         ELSIF ( set_reset='1' ) THEN
            next_state <= frozen_timing;
         END IF;

      WHEN paused =>
         IF ( start_stop='1' ) THEN
            next_state <= timing;
         ELSIF ( set_reset='1' ) THEN
            next_state <= cleared;
         END IF;

      WHEN frozen_timing =>
         IF ( start_stop='1' ) THEN
            next_state <= frozen_paused;
         ELSIF ( set_reset='1' ) THEN
            next_state <= timing;
         END IF;

      WHEN frozen_paused =>
         IF ( start_stop='1' ) THEN
            next_state <= frozen_timing;
         ELSIF ( set_reset='1' ) THEN
            next_state <= paused;
         END IF;

      WHEN OTHERS =>
         NULL;
      END CASE;

   END PROCESS set_next_state ;

   -------------------------------------------------------------------
   unclocked : PROCESS (
      current_state,
      current_time,
      current_time,
      current_time,
      paused_time,
      paused_time
   )
   -------------------------------------------------------------------
   BEGIN

      -- State Actions
      CASE current_state IS
      WHEN cleared =>
         indicator_mode<=solid;
         reset<='1';
         run_timer<='0';
         display_time<= current_time;
         pause_now <='0';
      WHEN timing =>
         indicator_mode<=solid;
         display_time <= current_time;
         run_timer<='1';
         reset<='0';
         pause_now<='0';
      WHEN paused =>
         indicator_mode<=solid;
         reset<='0';
         run_timer<='0';
         display_time <= current_time;
         pause_now<='0';
      WHEN frozen_timing =>
         reset<='0';
         run_timer<='1';
         display_time <= paused_time;
         indicator_mode<=blink;
         pause_now<='1';
      WHEN frozen_paused =>
         indicator_mode<=blink;
         display_time <= paused_time;
         run_timer<='0';
         reset<='0';
         pause_now<='1';
      WHEN OTHERS =>
         NULL;
      END CASE;

   END PROCESS unclocked ;
END state_machine ;

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