--
-- Component : timer
--
-- THIS CODE WRITTEN BY MICHAEL MAYER
-- Generated with System Architect version v8.4_3.7 by mrmayer on Feb 3, 1997
--
USE work.watch_functions.all;

ARCHITECTURE spec OF timer IS
BEGIN

   -------------------------------------------------------------------
   vhdl_timer : PROCESS (
      reset, run_timer, sys_clk  )
   -------------------------------------------------------------------
      VARIABLE prop_delay   : TIME := 1 ns;
      VARIABLE tick_no      : integer := 0;
      VARIABLE counter_time : time_stamp := (0,0,0,0,0,0);
      VARIABLE limit        : integer := 9;

   BEGIN
      if reset = '1' then
         counter_time := (0,0,0,0,0,0);
         tick_no := 0;
      elsif run_timer='1' and rising_edge(sys_clk) then
         if tick_no < 999 then
            tick_no := tick_no + 1;
         else
            tick_no := 0;
            for x in 1 to 6 loop
               if x = 4 then -- minutes can't go over 59
                  limit := 5;
               else
                  limit := 9;
               end if;  -- checking for minutes
               if counter_time(x) < limit then
                  counter_time(x) := counter_time(x) + 1;
                  exit;
               else 
                  counter_time(x) := 0;
                  next;
               end if;
            end loop;
         end if; --tick_no;
      end if;  -- reset / run_timer;
      current_time <= counter_time;
  END PROCESS vhdl_timer ;
END spec ;

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