-- -- component reg4 -- when enable is low, the register will output high impedance, -- but when it goes high, the register will store the value -- LIBRARY ieee; USE ieee.std_logic_1164.all; ARCHITECTURE struct OF reg4 IS COMPONENT d_latch is port ( d, clk : in std_logic; q : out std_logic ); END COMPONENT d_latch; COMPONENT tri_state_vector is port ( sel : IN std_logic; a,z : INOUT std_logic_vector ); END COMPONENT tri_state_vector; SIGNAL s : std_logic_vector (3 downto 0); SIGNAL en_compl : std_logic; BEGIN en_compl <= NOT enable; latch1 : COMPONENT d_latch PORT MAP ( d => data(0), clk => en_compl, q => s(0) ); latch2 : COMPONENT d_latch PORT MAP ( d => data(1), clk => en_compl, q => s(1) ); latch3 : COMPONENT d_latch PORT MAP ( d => data(2), clk => en_compl, q => s(2) ); latch4 : COMPONENT d_latch PORT MAP ( d => data(3), clk => en_compl, q => s(3) ); instance_tri_state_vector : COMPONENT tri_state_vector PORT MAP ( sel => enable, a => s, z => data ); END ARCHITECTURE struct;