SIMULATION REPORT Generated on Tue Apr 29 19:35:27 1997 Design simulated: cfg2 Number of signals in design: 392 Number of processes in design: 267 Simulator Parameters: Current directory: /home/classes/ws97/mrmayer/ee301hw/stopwatch VHDL Library: work Project file: quickvhdl.ini Simulation time resolution: us List of Design units used: Configuration: cfg_timer_struct Source File: cfg_timer_struct.vhd Configuration: cfg_disp_behav Source File: cfg_disp_behav.vhd Configuration: cfg2 Source File: cfg2.vhd Package Body: std_logic_1164 Source File: /mgc_user/pkgs/qvhdl_libs/src/std_logic_1164.vhd Package: standard Source File: /mgc_user/pkgs/qvhdl_libs/src/standard.vhd Entity: stopwatch Architecture: data_flow Source File: stopwatch_data_flow_a.vhd Entity: tick_tock Architecture: behavior Source File: ticktock.vhd Entity: disp_driver Architecture: struct Source File: disp_driver_struct_a.vhd Entity: segdecode Architecture: spec Source File: segdecode_spec_a.vhd Entity: main_control Architecture: struct Source File: main_control_struct_a.vhd Entity: dff Architecture: behavior Source File: dff_a.vhd Entity: switch_filter Architecture: struct Source File: switch_filter_struct_a.vhd Entity: filter Architecture: struct Source File: filter_a.vhd Entity: jkff Architecture: behavior Source File: jkff_a.vhd Entity: bcd_counter Architecture: struct Source File: bcd_counter_struct_a.vhd Entity: timer Architecture: struct Source File: timer_struct_a.vhd Entity: six_counter Architecture: struct Source File: six_counter_struct_a.vhd Entity: d_latch Architecture: behavior Source File: d_latch_a.vhd