LIBRARY ieee; USE ieee.std_logic_1164.all; ARCHITECTURE struct of bcd_counter is COMPONENT jkff IS port ( j, k, clk, reset : in std_logic; q : out std_logic ); END COMPONENT jkff; FOR ALL : jkff USE ENTITY work.jkff(behavior) PORT MAP ( j=>j, k=>k, clk=> clk, set=>open, reset=>reset, q=>q); SIGNAL clear, state10, x0, x1, x2, x3 : std_logic; SIGNAL clockprime, x0prime, x1prime, x2prime : std_logic; BEGIN clockprime <= NOT clock; x0prime <= NOT x0; x1prime <= NOT x1; X2prime <= NOT x2; stage1 : COMPONENT jkff port map ( j=>en, k=>en, clk=>clockprime, reset=>clear, q=>x0 ); stage2 : COMPONENT jkff port map ( j=>en, k=>en, clk=>x0prime, reset=>clear, q=>x1 ); stage3 : COMPONENT jkff port map ( j=>en, k=>en, clk=>x1prime, reset=>clear, q=>x2 ); stage4 : COMPONENT jkff port map ( j=>en, k=>en, clk=>x2prime, reset=>clear, q=>x3 ); q(0) <= x0; q(1) <= x1; q(2) <= x2; q(3) <= x3; sync <= x3 and (NOT x2) and x0; state10 <= x3 and (NOT x2) and x1; clear <= state10 or reset; END ARCHITECTURE struct;