LIBRARY ieee;  USE ieee.std_logic_1164.all;
ARCHITECTURE struct of six_counter is

   COMPONENT jkff IS
      port ( j, k, clk, reset : in std_logic;
             q : out std_logic );
   END COMPONENT jkff;

   FOR ALL : jkff 
      USE ENTITY work.jkff(behavior)
      PORT MAP ( j=>j, k=>k, clk=>clk, set=>open, reset=>reset, q=>q);

   SIGNAL clear, state6, x0, x1, x2 : std_logic; 

BEGIN

   stage1 : COMPONENT jkff
      port map ( j=>en, k=>en, clk=>clock, reset=>clear, q=>x0 );
    
   stage2 : COMPONENT jkff
      port map ( j=>en, k=>en, clk=>clock, reset=>clear, q=>x1 );
    
   stage3 : COMPONENT jkff
      port map ( j=>en, k=>en, clk=>clock, reset=>clear, q=>x2 );
    
   q(0) <= x0;
   q(1) <= x1;
   q(2) <= x2;
   sync <= x2 and (NOT x1) and x0;
   state6 <= x2 and x1; 
   clear <= state6 or reset;

END ARCHITECTURE struct;

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