LIBRARY ieee; USE ieee.std_logic_1164.all; architecture testbench_behav of testbench is component stopwatch is PORT ( sr_pressed : IN std_logic; ss_pressed : IN std_logic; sys_clk : IN std_logic; display_drv : OUT std_logic_vector (41 downto 0); indicators_on : OUT std_logic ); end component stopwatch; component tick_tock is generic ( PERIOD : time ); port ( clk: out std_logic); end component tick_tock; FOR dut : stopwatch USE CONFIGURATION work.cfg_stopwatch; signal clock : std_logic; signal ss, lr : std_logic; signal lcd_output : std_logic_vector (41 downto 0); signal indicators : std_logic; begin clock1 : component tick_tock generic map (10 us) port map (clock ); dut : component stopwatch port map (sys_clk => clock, ss_pressed => ss, sr_pressed => lr, display_drv => lcd_output, indicators_on => indicators ); end architecture testbench_behav;