-- -- Component : timer (structural) -- LIBRARY ieee; USE ieee.std_logic_1164.all; ARCHITECTURE struct OF timer IS COMPONENT bcd_counter is port ( clock, en, reset : in std_logic; sync : out std_logic; q : out std_logic_vector (3 downto 0) ); END COMPONENT bcd_counter; COMPONENT six_counter is port ( clock, en, reset : in std_logic; sync : out std_logic; q : out std_logic_vector (2 downto 0) ); END COMPONENT six_counter; COMPONENT d_latch is port (clk : in std_logic; d : in std_logic_vector; q : out std_logic_vector ); END COMPONENT d_latch; SIGNAL S1, S2, S3, S4, S5, S6, S7, S8 : std_logic; -- sync lines SIGNAL d1, d2, d3, d5, d6 : std_logic_vector (3 downto 0); -- data lines SIGNAL d4 : std_logic_vector (2 downto 0); SIGNAL dl_en : std_logic; BEGIN dl_en <= NOT latch_out; -- counters 1 - 9 c1 : bcd_counter -- hundred-thousandths (input from 100 KHZ sys_clk) PORT MAP ( clock => sys_clk, en => run_timer, reset => reset, sync => s1, q => open); c2 : bcd_counter -- ten-thousandths PORT MAP ( clock => s1, en => run_timer, reset => reset, sync => s2, q => open); c3 : bcd_counter -- thousandths PORT MAP ( clock => s2, en => run_timer, reset => reset, sync => s3, q => open); c4 : bcd_counter -- hundredths PORT MAP ( clock => s3, en => run_timer, reset => reset, sync => s4, q => d1); c5 : bcd_counter -- tenths PORT MAP ( clock => s4, en => run_timer, reset => reset, sync => s5, q => d2 ); c6 : bcd_counter -- seconds PORT MAP ( clock => s5, en => run_timer, reset => reset, sync => s6, q => d3 ); c7 : six_counter -- ten seconds PORT MAP ( clock => s6, en => run_timer, reset => reset, sync => s7, q => d4 ); c8 : bcd_counter -- minutes PORT MAP ( clock => s7, en => run_timer, reset => reset, sync => s8, q => d5 ); c9 : bcd_counter -- ten minutes PORT MAP ( clock => s8, en => run_timer, reset => reset, sync => open, q => d6 ); -- tri-state 1-6 t1 : d_latch -- hundredths PORT MAP (clk => dl_en, d => d1, q => time_data(3 downto 0) ); t2 : d_latch -- tenths PORT MAP (clk => dl_en, d => d2, q => time_data(7 downto 4) ); t3 : d_latch -- seconds PORT MAP (clk => dl_en, d => d3, q => time_data(11 downto 8) ); t4 : d_latch -- ten seconds PORT MAP (clk => dl_en, d => d4, q => time_data(14 downto 12) ); t5 : d_latch -- minutes PORT MAP (clk => dl_en, d => d5, q => time_data(18 downto 15) ); t6 : d_latch -- ten minutes PORT MAP (clk => dl_en, d => d6, q => time_data(22 downto 19) ); END architecture struct;