--
-- Rcsid[] = "$Id: bc_pc_sp.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--
 
-- This module contains the BC register pair, the PC and SP, and their
-- respective write enable and out enable.  Each pair feeds into two
-- busses(an 8 bit and a 16 bit bus).

entity bc_pc_sp is
port(B16BO:out bit_vector(0 to 15);
     B8BO :out bit_vector(0 to 7);
     D: in bit_vector(0 to 15);
     WRB,WRC,WRBC,WRPCH,WRPCL,WRPC,BOUT,COUT,BCOUT,PCHOUT,PCLOUT,PCOUT,
     SP0OUT,SP1OUT,SPOUT,WRSP0,WRSP1,WRSP,CLK,VCC,RESETPC: in bit);
end;

architecture structure of bc_pc_sp is

component regpairs
port(Q: out bit_vector(0 to 15);
     D: in  bit_vector(0 to 15);
     CLEAR,VCC,WRLOW,WRHIGH,WRBOTH,CK: in bit);
end component;

component ocnand
port(O: out bit_vector(7 downto 0);
     I: in bit_vector(7 downto 0);
     ENABLE: in bit);
end component;

signal qb: bit_vector(0 to 15);
signal qp: bit_vector(0 to 15);
signal qs: bit_vector(0 to 15);

begin
BC : REGPAIRS port map(qb(0 to 15),D(0 to 15),VCC,    VCC,WRC,  WRB,  WRBC,CLK);
PC : REGPAIRS port map(qp(0 to 15),D(0 to 15),RESETPC,VCC,WRPCL,WRPCH,WRPC,CLK);
SP : REGPAIRS port map(qs(0 to 15),D(0 to 15),VCC,    VCC,WRSP0,WRSP1,WRSP,CLK);

U3  : OCNAND port map(B16BO(0 to 7),  qb(0 to 7), BCOUT);
U4  : OCNAND port map(B16BO(8 to 15), qb(8 to 15),BCOUT);
U7  : OCNAND port map(B8BO (0 to 7),  qb(0 to 7), COUT);
U8  : OCNAND port map(B8BO (0 to 7),  qb(8 to 15),BOUT);

U5  : OCNAND port map(B16BO(0 to 7),  qp(0 to 7), PCOUT);
U6  : OCNAND port map(B16BO(8 to 15), qp(8 to 15),PCOUT);
U9  : OCNAND port map(B8BO (0 to 7),  qp(0 to 7), PCLOUT);
U10 : OCNAND port map(B8BO (0 to 7),  qp(8 to 15),PCHOUT);

U11 : OCNAND port map(B8BO (0 to 7),  qs(0 to 7), SP0OUT);
U12 : OCNAND port map(B8BO (0 to 7),  qs(8 to 15),SP1OUT);
U13 : OCNAND port map(B16BO(0 to 7),  qs(0 to 7), SPOUT);
U14 : OCNAND port map(B16BO(8 to 15), qs(8 to 15),SPOUT);
end structure;

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