--
-- Rcsid[] = "$Id: g16bctr.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";

--
--------------------------------------------------
--  g16bctr.vhd
--  May 24, 1993
--------------------------------------------------
--

--  This is the 16 bit address incrementer/decrementer latch.
--  It is also used to temporarily hold the address for some
--  instructions, such as IN, OUT, LHLD, etc.

entity g16bctr is
port(Outt: out bit_vector(0 to 15);
     D: in bit_vector(0 to 15);
     clk , loadall, outen, INCR, DECR, RESET, VCC: in bit);
end;

architecture structure of g16bctr is

component g4bctr
port(QD,QC,QB,QA,carry: out bit;
     dataD,dataC,dataB,dataA,clk,UD,load,enP,enT,VCC: in bit);
end component;

component ocnand
port(O: out bit_vector(0 to 7);
     I: in  bit_vector(0 to 7);
     ENABLE: in bit);
end component;

signal net0, net1, net3, net6, net9, net12: bit;
signal Q: bit_vector(15 downto 0);
signal rc1, rc2, rc3: bit;

begin
U0 : nor_gate generic map (1,1) port map(net0,INCR,DECR);
U1 : inv_gate generic map (1,1) port map(net1,DECR);
U3 : and_gate generic map (1,1) port map(net3,loadall,RESET);
U4 : g4bctr port map(Q(3 downto 0),
                 rc1,D(3),D(2),D(1),D(0),clk,net1,net3,net0,net0,VCC);
U6 : and_gate generic map (1,1) port map(net6,loadall,RESET);
U7 : g4bctr port map(Q(7 downto 4),
                 rc2,D(7),D(6),D(5),D(4),clk,net1,net6,rc1,rc1,VCC);
U9 : and_gate generic map (1,1) port map(net9,loadall,RESET);
U10 : g4bctr port map(Q(11 downto 8),
                 rc3,D(11),D(10),D(9),D(8),clk,net1,net9,rc2,rc2,VCC);
U12 : and_gate generic map (1,1) port map(net12,loadall,RESET);
U13 : g4bctr port map(Q(15 downto 12),
                 OPEN,D(15),D(14),D(13),D(12),clk,net1,net12,rc3,rc3,VCC);
U14 : ocnand port map(Outt(0  to 7),Q(0),Q(1),Q(2),Q(3),Q(4),Q(5),Q(6),Q(7),outen);
U15 : ocnand port map(Outt(8 to 15),Q(8),Q(9),Q(10),Q(11),Q(12),Q(13),Q(14),Q(15),outen);
end structure;

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