--
-- Rcsid[] = "$Id: rdwrgen.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

---------------------------------------------
--  May 22, 1993
--  RDWRGEN
---------------------------------------------

-- read-write control signals generator
-- This module is responsible for generating the read,write,ALE,
-- INTABAR,S1,S0,and IOMBAR signals.

entity rdwrgen is
port(ALE,RDBAR,WRBAR,INTABAR,IOMBAR,S1,S0,BIMC: out bit;
     T3,T2,T1,CLKBAR,CLK,wrinm2,wrinm3,ID19,ID16,ID15,ID13,
     ID11,ID10,ID9,ID5,ID4,ID3,ID2,ID1,I3,
     INA,INTA,CCBAR,RESETBAR,VCC: in bit;
     M: in bit_vector(5 downto 1));
end;

architecture structure of rdwrgen is

signal n1, n2, n3, n4, n5, n6, n7, n8, n9: bit;
signal n11, n12, n13, n14, n17, n18, n19: bit;
signal n20, n21, n23, n24, n29: bit;
signal n30, n34, n36: bit;
signal n37, n38, n39, n40, n44, n45, n45a, n54: bit;
signal ZZ1, zzz1, ZZ2, zzz2, ZZ3, zzz3: bit;
signal FF1QBAR, FF2QBAR, FF3QBAR: bit;
signal CALL,CALLCOND,n19b,n19c,n19d,n19e: bit;
signal C17, BIMCB: bit;

begin
U1 : inv_gate generic map(2,2) port map(n1,M(1));
U2 : inv_gate generic map(2,2) port map(n2,T2);
U3 : or_gate generic map(2,2) port map(n3,T3,CLK);
U4 : or_gate generic map(2,2) port map(n4,M(3),wrinm3);
U5 : or_gate generic map(2,2) port map(n5,wrinm2,M(2));
U6 : or_gate generic map(2,2) port map(n6,ID16,ID2);
U7 : and_gate generic map(2,2) port map(n7,M(4),M(5));
U8 : inv_gate generic map(2,2) port map(n8,M(2));
U9 : inv_gate generic map(2,2) port map(n9,M(3));
U11 : and_gate generic map(2,2) port map(n11,CLKBAR,n2);
U12 : and_gate generic map(2,2) port map(n12,RESETBAR,n3);
U13 : or_gate generic map(2,2) port map(n13,n6,ID15,M(4));
U14 : or_gate generic map(2,2) port map(n14,n6,ID13,n7);
U17 : and_gate generic map(2,2) port map(n17,n1,INA);
U18 : nor_gate generic map(2,2) port map(n18,C17,n1);
U19 : nand_gate generic map(2,2) port map(n19,n4,n5,n13,n14,CALL,CALLCOND);
U19a : OR_gate port map(CALL,ID19,ID9,ID5);  -- CALL
u19b : NOR_gate port map(n19b,CALL,M(2));
u19c : NOR_gate port map(n19c,CALL,M(3));
u19d : or_gate generic map (2,2) port map(CALLCOND,ID19,ID4,CCBAR);
u19e : NOR_gate port map(n19d,CALLCOND,M(2));
u19f : NOR_gate port map(n19e,CALLCOND,M(3));
U20 : and_gate generic map(2,2) port map(n20,n8,wrinm2);
U21 : and_gate generic map(2,2) port map(n21,n9,wrinm3);
U23 : and_gate generic map(2,2) port map(n23,n45,n44);
U24 : or_gate generic map(2,2) port map(n24,n20,n21,n23);
U25 : DFF1 port map(zzz1,n1,n11,VCC,n12);
u25a : inv_gate port map(ZZ1,zzz1);
U26 : DFF1 port map(zzz2,n19,n11,VCC,n12);
u26a : inv_gate port map(ZZ2,zzz2);
U27 : DFF1 port map(zzz3,n24,n11,VCC,n12);
u27a : inv_gate port map(ZZ3,zzz3);
U28 : or_gate generic map(2,2) port map(BIMCB,n18,n17);
U28A : BUF_gate port map (BIMC,BIMCB);
U29 : and_gate generic map(2,2) port map(n29,FF1QBAR,FF2QBAR);
U30 : inv_gate generic map(2,2) port map(n30,INTA);
U31 : nor_gate generic map(2,2) port map(ALE,CLKBAR,T1,BIMCB);
U32 : or_gate generic map(2,2) port map(RDBAR,BIMCB,n29,INTA);
U33 : or_gate generic map(2,2) port map(INTABAR,n29,n30);
U34 : inv_gate generic map(2,2) port map(n34,C17);
U35 : or_gate generic map(2,2) port map(WRBAR,FF3QBAR,n34,n19b,n19c,n19d,n19e);
U36 : or_gate generic map(2,2) port map(n36,ID19,ID3);
U37 : nor_gate generic map(2,2) port map(n37,n36,ID11);
U38 : nor_gate generic map(2,2) port map(n38,n36,ID10);
U39 : and_gate generic map(2,2) port map(n39,n19,n37);
U40 : and_gate generic map(2,2) port map(n40,n24,n38);
U41 : or_gate generic map(2,2) port map(IOMBAR,n39,n40,INTA,n17);
U42 : or_gate generic map(2,2) port map(S1,n1,n19,INTA,n18);
U43 : or_gate generic map(2,2) port map(S0,n1,n24,INTA);
U44 : inv_gate generic map(1,1) port map(n44,n7);
U45 : or_gate generic map(1,1) port map(n45,n6,n45a);
U45a : and_gate generic map(1,1) port map(n45a,ID13,ID15);
U50 : buf_gate generic map(2,2) port map(FF1QBAR,ZZ1);
U51 : buf_gate generic map(2,2) port map(FF2QBAR,ZZ2);
U52 : buf_gate generic map(2,2) port map(FF3QBAR,ZZ3);
U53 : or_gate generic map(2,2) port map(C17,ID16,ID1,n54);
U54 : inv_gate generic map(1,1) port map(n54,I3);
end structure;

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