-- -- Rcsid[] = "$Id: regctrl1.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $"; -- --------------------------------------------- -- regctrl1.vhd -- June 19, 1993 --------------------------------------------- entity regctrl1 is port(DECRLATCH,INCRLATCH,SEL16BUS,WRBC,WRDE,WRHL,WRSP,BCOUT,DEOUT, HLOUT,SPOUT,BOUT,COUT,DOUT,EOUT,HOUT,LOUT,SP0OUT,SP1OUT,WRB, WRC,WRD,WRE,WRH,WRL,WRSP0,WRSP1,WRAUXACC,WRAUXACC1,LOADLATCH, XCHGT4,XCHGT1: out bit; ID0,ID1,ID2,ID3,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,ID12,ID13, ID15,ID16,ID18,ID19,I3,I4,I5,M1,M2,M3,M4, T1,T2,T3,T4,T5,T6,CCBAR,VCC: in bit); end; architecture structure of regctrl1 is component decod2_4 port(O: out bit_vector(3 downto 0); I: in bit_vector(1 downto 0)); end component; signal rp: bit_vector(3 downto 0); signal n2, n3, n4, n10, n11, n12: bit; signal n17, M2T1,M3T1 : bit; signal n31, n33, n36, n38, n39 : bit; signal n42, n44, n45, n46: bit; signal n60, n62: bit; signal n80, n81, n97: bit; signal SPHL, PSHR, RST, M1T5, M2T2, M2T3, M3T2, M3T3, M4T2, M2T2M3T2, M1T5M4T2 : bit; signal PUSH, POP_RP, POP_SP , CALL, CALLCOND: bit; signal WRDE1, WRHL1, DAD, COUTd, EOUTd, LOUTd, BOUTd, DOUTd, HOUTd: bit; signal M1T5M2T2, BOUTp, DOUTp, HOUTp, COUTp, EOUTp, LOUTp: bit; signal INR, INRDCR, M1T4, XTHL, LXI, WRCl, WREl, WRLl, WRBl, WRDl, WRHll: bit; signal WRCp, WREp, WRLp, WRBp, WRDp, WRHp, WRAUXACC2: bit; signal XCHGT1_buf,XCHGT4_buf,WRAUXACC1_buf: bit; signal n200,n201,n202, ALU_OPS: bit; signal Rcond, RSTx: bit; signal n19b,n19e: bit; signal n86n,n22a,n22b,n51a,n51b,n80a,n80b,n100a,n100b: bit; begin U0 : decod2_4 port map(rp(3),rp(2),rp(1),rp(0),I5,I4); U1 : or_gate generic map(1,1) port map(INR,ID16,ID4); U2 : nor_gate generic map(1,1) port map(n2,INR,T4); U3 : nor_gate generic map(1,1) port map(n3,INR,T5); U4 : inv_gate generic map(1,1) port map(n4,I3); U5 : and_gate generic map(1,1) port map(DECRLATCH,I3,n3); U6 : BUF_gate generic map(1,1) port map(INCRLATCH,n3); U7 : nor_gate generic map(1,1) port map(XCHGT1_buf,ID19,ID13,ID3,T1); U7a : buf_gate port map (XCHGT1,XCHGT1_buf); U8 : nor_gate generic map(1,1) port map(SPHL,ID19,ID15,ID1,T4); U81p : nor_gate generic map(1,1) port map(PSHR,ID19,ID5,I3,M1T5M2T2); -- PUSH rp / PUSH PSW U81q : NOR_gate generic map(1,1) port map(RST, ID19,ID7,M1T5M2T2); -- RST U81r : NOR_gate generic map(1,1) port map(CALL,ID19,ID5,ID9,M1T5M4T2); -- CALL u81s : NOR_gate generic map (1,1) port map(CALLCOND,ID19,ID4,CCBAR,M1T5M4T2); -- CALL Conditional U82p : and_gate generic map(1,1) port map(M1T5M2T2,M1T5,M2T2); U34 : or_gate generic map(1,1) port map(M1T4,M1,T4); U83p : or_gate generic map(1,1) port map(M1T5,M1,T5); U84p : or_gate generic map(1,1) port map(M2T2,M2,T2); U85p : or_gate generic map(1,1) port map(M3T2,M3,T2); U85q : or_gate generic map(1,1) port map(M4T2,M4,T2); U85r : and_gate generic map(1,1) port map(M1T5M4T2,M1T5,M4T2); U86n : or_gate port map(n86n,ID19,ID1,I3); -- POP rp U86p : nor_gate generic map(1,1) port map(POP_SP,n86n,M2T2M3T2); -- POP rp -- POP PSW U86pp : inv_gate generic map(1,1) port map(POP_RP,n86n); -- POP rp -- POP PSW U87p : and_gate generic map(1,1) port map(M2T2M3T2,M2T2,M3T2); U9 : or_gate generic map(1,1) port map(SEL16BUS,SPHL,XCHGT1_buf,RSTx); U9a : NOR_gate port map(RSTx,ID19,ID7,M3,T2); -- load W,Z in M3,T2 from bus U10 : and_gate generic map(1,1) port map(n10, rp(0),n2); U11 : and_gate generic map(1,1) port map(n11, rp(1),n2); U12 : and_gate generic map(1,1) port map(n12, rp(2),n2); U13 : and_gate generic map(1,1) port map(SPOUT,rp(3),n2); U14 : and_gate generic map(1,1) port map(WRBC, rp(0),n3); U15 : and_gate generic map(1,1) port map(WRDE1,rp(1),n3); U16 : and_gate generic map(1,1) port map(WRHL1,rp(2),n3); U17 : and_gate generic map(1,1) port map(n17,rp(3),n3); U18 : or_gate generic map(1,1) port map(HLOUT,n12,SPHL); U19 : or_gate generic map(1,1) port map(WRSP,n17,SPHL,PSHR,POP_SP,RST,CALL,CALLCOND,n19b,n19e); U19b : NOR_gate generic map(1,1) port map(n19b,ID19,ID9,ID1,M2T2M3T2); -- RET U19d : OR_gate generic map(1,1) port map(Rcond,ID19,ID0,CCBAR); U19e : NOR_gate generic map(1,1) port map(n19e,Rcond,M2T2M3T2); -- CONTROL LOGIC FOR THE DAD INSTRUCTION U20 : nor_gate generic map(1,1) port map(M2T1,M2,T1); U21 : nor_gate generic map(1,1) port map(M3T1,M3,T1); U22 : nor_gate generic map(1,1) port map(DAD,ID16,ID1,n4); -- decoding DAD U22a : AND_gate port map(n22a,DAD,M2T1); U22b : AND_gate port map(n22b,DAD,M3T1); U23 : and_gate generic map(1,1) port map(COUTd, rp(0),n22a); U24 : and_gate generic map(1,1) port map(EOUTd, rp(1),n22a); U25 : and_gate generic map(1,1) port map(LOUTd, rp(2),n22a); U26 : and_gate generic map(1,1) port map(SP0OUT,rp(3),n22a); U27 : and_gate generic map(1,1) port map(BOUTd, rp(0),n22b); U28 : and_gate generic map(1,1) port map(DOUTd, rp(1),n22b); U29 : and_gate generic map(1,1) port map(HOUTd, rp(2),n22b); U30 : and_gate generic map(1,1) port map(SP1OUT,rp(3),n22b); -- CONTROL LOGIC FOR THE PUSH INSTRUCTION --U80 : nor_gate generic map(1,1) port map(n80,M2,T2); --U81 : nor_gate generic map(1,1) port map(n81,M3,T2); U80 : inv_gate generic map(1,1) port map(n80,M2T2); U80a : AND_gate port map(n80a,PUSH,n80); U80b : AND_gate port map(n80b,PUSH,n81); U81 : inv_gate generic map(1,1) port map(n81,M3T2); U82 : nor_gate generic map(1,1) port map(PUSH,ID19,ID5,I3); -- decoding PUSH U83 : and_gate generic map(1,1) port map(BOUTp,rp(0),n80a); U84 : and_gate generic map(1,1) port map(DOUTp,rp(1),n80a); U85 : and_gate generic map(1,1) port map(HOUTp,rp(2),n80a); U86 : and_gate generic map(1,1) port map(COUTp,rp(0),n80b); U87 : and_gate generic map(1,1) port map(EOUTp,rp(1),n80b); U88 : and_gate generic map(1,1) port map(LOUTp,rp(2),n80b); U90 : or_gate generic map(1,1) port map(COUT,COUTp,COUTd); U91 : or_gate generic map(1,1) port map(EOUT,EOUTp,EOUTd); U92 : or_gate generic map(1,1) port map(LOUT,LOUTp,LOUTd); U93 : or_gate generic map(1,1) port map(BOUT,BOUTp,BOUTd); U94 : or_gate generic map(1,1) port map(DOUT,DOUTp,DOUTd); U95 : or_gate generic map(1,1) port map(HOUT,HOUTp,HOUTd); -- CONTROLLING AUXACC U31 : and_gate generic map(1,1) port map(n31,ID4,ID5); U32 : nor_gate generic map(1,1) port map(INRDCR,ID16,n31); U33 : and_gate generic map(1,1) port map(n33,M1T4,INRDCR); U35 : or_gate generic map(1,1) port map(WRAUXACC1_buf,n33,n38,n36); -- n96 U35a : buf_gate port map (WRAUXACC1,WRAUXACC1_buf); U36 : nor_gate generic map(1,1) port map(n36,T3,M3,XTHL); U37 : or_gate generic map(1,1) port map(XTHL,ID19,ID12,ID3); U38 : nor_gate generic map(1,1) port map(n38,n62,T1,n39); U39 : and_gate generic map(1,1) port map(n39,M2,M3); -- PUSH -- U91s : and_gate generic map(1,1) port map(SELPSH,PUSH,n8081); -- U92s : or_gate generic map(1,1) port map(n8081,n80,n81); -- LDAX STAX INSTRUCTION CONTROL U42 : or_gate generic map(1,1) port map(n42,ID16,ID2); U44 : nor_gate generic map(1,1) port map(n44,M1T4,n42); U45 : and_gate generic map(1,1) port map(n45,rp(0),n44); -- BCOUT U46 : and_gate generic map(1,1) port map(n46,rp(1),n44); -- DEOUT U47 : or_gate generic map(1,1) port map(BCOUT,n10,n45); U48 : or_gate generic map(1,1) port map(DEOUT,n11,n46); -- LXI,INSTRUCTION U49 : nor_gate generic map(1,1) port map(LXI,ID16,ID1,I3); U50 : nor_gate generic map(1,1) port map(M2T3,M2,T3); U51 : nor_gate generic map(1,1) port map(M3T3,M3,T3); U51a : AND_gate port map(n51a,M2T3,LXI); U51b : AND_gate port map(n51b,M3T3,LXI); U52 : and_gate generic map(1,1) port map(WRCl, rp(0),n51a); U53 : and_gate generic map(1,1) port map(WREl, rp(1),n51a); U54 : and_gate generic map(1,1) port map(WRLl, rp(2),n51a); U55 : and_gate generic map(1,1) port map(WRSP0,rp(3),n51a); U56 : and_gate generic map(1,1) port map(WRBl, rp(0),n51b); U57 : and_gate generic map(1,1) port map(WRDl, rp(1),n51b); U58 : and_gate generic map(1,1) port map(WRHll,rp(2),n51b); U59 : and_gate generic map(1,1) port map(WRSP1,rp(3),n51b); U100a : and_gate port map(n100a,M2T3,POP_RP); U100b : and_gate port map(n100b,M3T3,POP_RP); U100 : and_gate generic map(1,1) port map(WRCp,rp(0),n100a); U101 : and_gate generic map(1,1) port map(WREp,rp(1),n100a); U102 : and_gate generic map(1,1) port map(WRLp,rp(2),n100a); U103 : and_gate generic map(1,1) port map(WRBp,rp(0),n100b); U104 : and_gate generic map(1,1) port map(WRDp,rp(1),n100b); U105 : and_gate generic map(1,1) port map(WRHp,rp(2),n100b); U106 : or_gate generic map(1,1) port map(WRC,WRCp,WRCl); U107 : or_gate generic map(1,1) port map(WRE,WREp,WREl); U108 : or_gate generic map(1,1) port map(WRL,WRLp,WRLl); U109 : or_gate generic map(1,1) port map(WRB,WRBp,WRBl); U110 : or_gate generic map(1,1) port map(WRD,WRDp,WRDl); U111 : or_gate generic map(1,1) port map(WRH,WRHp,WRHll); -- LOAD PC AFTER THE INX DCX INSTRUCTION U60 : nor_gate generic map(1,1) port map(n60,INR,T6); U61 : or_gate generic map(1,1) port map(LOADLATCH,n60,n2); -- invert DAD signal for WRACCAUX U62 : inv_gate generic map(1,1) port map(n62,DAD); U63 : or_gate generic map(1,1) port map(WRHL,WRHL1,XCHGT4_buf); U64 : or_gate generic map(1,1) port map(WRDE,WRDE1,XCHGT1_buf); U65 : nor_gate generic map(1,1) port map(XCHGT4_buf,ID19,ID13,ID3,T4); U65a : buf_gate port map (XCHGT4,XCHGT4_buf); -- The following logic is timing sensitive, gate delays must -- not be changed until the circuit is made fully synchronous. U68 : NOR_gate generic map(2,2) port map(WRAUXACC2,M1T4,n200); U200 : AND_gate generic map(0,0) port map(n200,ALU_OPS,n202); U201 : OR_gate generic map(0,0) port map(n201,ID19,ID6); U202 : OR_gate generic map(0,0) port map(n202,ID16,ID7,n97); U203 : AND_gate generic map(0,0) port map(ALU_OPS,ID18,n201); U69 : or_gate generic map(1,1) port map(WRAUXACC,WRAUXACC1_buf,WRAUXACC2); U97 : and_gate generic map(1,1) port map(n97,ID8,ID9,ID10,ID11,ID13); end structure;