--
-- Rcsid[] = "$Id: regpad.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity regpad is
port(B16BO: out bit_vector(0 to 15);
     B8BO:  out bit_vector(0 to 7);
	 B16Bin: in bit_vector(0 to 15);
	 B8Bin: in bit_vector(0 to 7);
     sel16,SEL_CNTR,WRB,WRC,WRBC,WRPCH,WRPCL,WRPC,
	 BOUT, COUT,BCOUT,PCHOUT,PCLOUT,PCOUT,
	 RESETPC,WRH,WRL,WRHL,WRD,WRE,WRDE,
     HOUT,LOUT,HLOUT,DOUT,EOUT,DEOUT,
     ID19,ID13,ID3,loadctrall_not,
     ctrouten,INCR,DECR:        in bit;
     SP0OUT,SP1OUT,SPOUT, WRSP0,WRSP1,WRSP,CLK,LATCHCLK,WRZ,
     WRW,WZOUT,WRWZ,T4,GND,VCC: in bit);
end;

architecture structure of regpad is

component mux_4bit
port(Y: out bit_vector(0 to 3);
     A,B: in bit_vector(0 to 3);
     choose: in bit);
end component;

component bc_pc_sp
port(B16BO:out bit_vector(0 to 15);
     B8BO :out bit_vector(0 to 7);
     D: in bit_vector(0 to 15);
     WRB,WRC,WRBC,WRPCH,WRPCL,WRPC,BOUT,COUT,BCOUT,PCHOUT,PCLOUT,PCOUT,
     SP0OUT,SP1OUT,SPOUT,WRSP0,WRSP1,WRSP,CLK,VCC,RESETPC: in bit);
end component;

component hl_de_wz
port(B16BO: out bit_vector(0 to 15);
     B8BO:  out bit_vector(0 to 7);
     D: in bit_vector(0 to 15);
     WRH,WRL,WRHL,WRD,WRE,WRDE,HOUT,LOUT,HLOUT,DOUT,EOUT,DEOUT,CLK,
     ID19,ID3,ID13,WRZ,WRW,WZOUT,WRWZ,T4,GND,VCC: in bit);
end component;

component g16bctr
port(Outt: out bit_vector(0 to 15);
     D: in bit_vector(0 to 15);
     clk, loadall, outen, INCR, DECR, RESET, VCC: in bit);
end component;

signal dn: bit_vector(0 to 15);
signal ddn: bit_vector(0 to 15);
signal loadctrall: bit;

begin
U1 : mux_4bit port map(dn(0 to 3),  B8Bin(0 to 3),B16Bin(0 to 3),  sel16);
U2 : mux_4bit port map(dn(4 to 7),  B8Bin(4 to 7),B16Bin(4 to 7),  sel16);
U3 : mux_4bit port map(dn(8 to 11) ,B8Bin(0 to 3),B16Bin(8 to 11), sel16);
U4 : mux_4bit port map(dn(12 to 15),B8Bin(4 to 7),B16Bin(12 to 15),sel16);
U5 : inv_gate generic map(1,1) port map(loadctrall,loadctrall_not);

BCPS : bc_pc_sp port map(B16BO(0 to 15),B8BO(0 to 7), dn(0 to 15),
        WRB,WRC,WRBC,WRPCH,WRPCL,WRPC,BOUT,COUT,
        BCOUT,PCHOUT,PCLOUT,PCOUT,SP0OUT,SP1OUT,SPOUT,
        WRSP0,WRSP1,WRSP,CLK,VCC,RESETPC);

HLDEW : hl_de_wz port map(B16BO(0 to 15),B8BO(0 to 7), dn(0 to 15),
        WRH,WRL,WRHL,WRD,WRE,WRDE,HOUT,LOUT,HLOUT,
        DOUT,EOUT,DEOUT,CLK,ID19,ID3,ID13,
        WRZ,WRW,WZOUT,WRWZ,T4,GND,VCC);

G16CTR : g16bctr port map(B16BO(0 to 15), ddn(0 to 15),
        LATCHCLK,loadctrall,ctrouten,INCR,DECR,RESETPC,VCC);
X0  : AND_gate generic map(1,1) port map (ddn(0), B16Bin(0), sel_cntr);
X1  : AND_gate generic map(1,1) port map (ddn(1), B16Bin(1), sel_cntr);
X2  : AND_gate generic map(1,1) port map (ddn(2), B16Bin(2), sel_cntr);
X3  : AND_gate generic map(1,1) port map (ddn(3), B16Bin(3), sel_cntr);
X4  : AND_gate generic map(1,1) port map (ddn(4), B16Bin(4), sel_cntr);
X5  : AND_gate generic map(1,1) port map (ddn(5), B16Bin(5), sel_cntr);
X6  : AND_gate generic map(1,1) port map (ddn(6), B16Bin(6), sel_cntr);
X7  : AND_gate generic map(1,1) port map (ddn(7), B16Bin(7), sel_cntr);
X8  : AND_gate generic map(1,1) port map (ddn(8), B16Bin(8), sel_cntr);
X9  : AND_gate generic map(1,1) port map (ddn(9), B16Bin(9), sel_cntr);
X10 : AND_gate generic map(1,1) port map (ddn(10),B16Bin(10),sel_cntr);
X11 : AND_gate generic map(1,1) port map (ddn(11),B16Bin(11),sel_cntr);
X12 : AND_gate generic map(1,1) port map (ddn(12),B16Bin(12),sel_cntr);
X13 : AND_gate generic map(1,1) port map (ddn(13),B16Bin(13),sel_cntr);
X14 : AND_gate generic map(1,1) port map (ddn(14),B16Bin(14),sel_cntr);
X15 : AND_gate generic map(1,1) port map (ddn(15),B16Bin(15),sel_cntr);
end structure;

<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br />&nbsp;</div>