--
-- Rcsid[] = "$Id: sn85150.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- The STATE vector selects one of ten inputs to pass through
-- to the output.
--
entity SN85150 is
port(out_z: out bit;
	e0, e1, e2, e3, e4, e5, e6, e7: in bit;
	e8, e9: in bit;
	STATE: in bit_vector(3 downto 0));
end;

architecture structure of SN85150 is

signal abar, bbar, cbar, dbar: bit;
signal d0, d1, d2, d3, d4, d5, d6, d7, d8, d9: bit;
signal az, bz, cz, dz : bit;

begin
U1 : INV_gate generic map(1,1) port map(abar,STATE(0));
U2 : INV_gate generic map(1,1) port map(bbar,STATE(1));
U3 : INV_gate generic map(1,1) port map(cbar,STATE(2));
U4 : INV_gate generic map(1,1) port map(dbar,STATE(3));
U5 : INV_gate generic map(1,1) port map(az,abar);
U6 : INV_gate generic map(1,1) port map(bz,bbar);
U7 : INV_gate generic map(1,1) port map(cz,cbar);
U8 : INV_gate generic map(1,1) port map(dz,dbar);
U10 : AND_gate port map(d0,e0,abar,bbar,cbar,dbar);
U11 : AND_gate port map(d1,e1,az,bbar,cbar,dbar);
U12 : AND_gate port map(d2,e2,abar,bz,cbar,dbar);
U13 : AND_gate port map(d3,e3,az,bz,cbar,dbar);
U14 : AND_gate port map(d4,e4,abar,bbar,cz,dbar);
U15 : AND_gate port map(d5,e5,az,bbar,cz,dbar);
U16 : AND_gate port map(d6,e6,abar,bz,cz,dbar);
U17 : AND_gate port map(d7,e7,az,bz,cz,dbar);
U18 : AND_gate port map(d8,e8,abar,bbar,cbar,dz);
U19 : AND_gate port map(d9,e9,az,bbar,cbar,dz);
U26 : OR_gate generic map(3,3) port map(out_z,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9);
end structure;

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