---------------------------------------------------------------------------
-- Copyright SAAB ERICSSON SPACE AB --
---------------------------------------------------------------------------
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Library General Public License for more details.
-- You should have received a copy of the GNU Library General Public
-- License along with this library; if not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
---------------------------------------------------------------------------
-- Title:
-- File name:
-- VHDL unit: (Type)
-- Purpose and functionality: (Text)
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
-- SAAB ERICSSON SPACE AB --
-- Delsjomotet Phone Int: +46 31 35 00 00 --
-- S-405 15 GOTHENBURG Fax Int: +46 31 35 95 20 --
-- Sweden Telex: 27950 saabsp s --
---------------------------------------------------------------------------
--
--
library IEEE;
use IEEE.Std_Logic_1164.all;
library MMS;
use MMS.StdRTL.all;
package MECPackage is
type UX01_Vector is array (natural range <>) of UX01;
--- Subtype used in the EDAC
subtype CheckBits is std_logic_Vector ( 6 downto 0 );
subtype SyndromBits is std_logic_Vector ( 7 downto 0 );
subtype DataBits is std_logic_Vector ( 31 downto 0 );
function ParityGen(Val : Std_Logic_Vector) return UX01;
function ParityCheck(Val: Std_Logic_Vector; Parity: UX01)
return UX01;
function Decrement(Val : Std_Logic_Vector) return Std_Logic_Vector;
-- function Hex2Vec(HexInput: string; Width: positive)
-- return Std_Logic_Vector;
-- function To_UX01_Vector (Input: Std_Logic_Vector)
-- return UX01_vector;
-- This function is not used and therfore removed
function Bool_To_UX01 (Val : Boolean) return UX01;
function Vector_OR ( Data : Std_Logic_Vector ) return UX01;
-- function Bit_And_Vector ( Bit : UX01; Vec : Std_Logic_Vector) return Std_Logic_Vector;
-- This function is not used and therfore removed
function Compare (A,B : Std_Logic_Vector) return UX01;
--- Generate check bits
function ChkGen ( Data : in DataBits ) return CheckBits;
--- Generate syndrom bits
function SyndromGen ( ChkBits_In : CheckBits;
Chk_Ok : CheckBits;
Parity : std_logic ) return SyndromBits;
function SyndromGenS ( ChkBits_In : CheckBits;
Chk_Ok : CheckBits;
Chk_Ok7 : std_logic;
Parity : std_logic ) return SyndromBits;
function Correct_Data ( Syndrom : in SyndromBits;
Data : in Std_logic_vector ) return std_logic_vector;
function NCError_Gen ( Syndrom : in SyndromBits ) return std_logic;
function CError_Gen ( Syndrom : in SyndromBits ) return std_logic;
end MECPackage;
---------------------------------------------------------------------------
package body MECPackage is
type Logic_UX01_Table is array (Std_ulogic'low to Std_ulogic'high) of UX01;
constant Cvt_To_UX01 : Logic_UX01_Table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
---------------------------------------------------------------------------
function ParityGen(Val : Std_Logic_Vector) return UX01 is
--Normalize the indexing
alias Data : Std_Logic_Vector(Val'length downto 1) is Val;
variable Result : UX01 := '1';
begin
for K in 1 to Data'length loop
Result := Result xor Data(K);
end loop;
return Result;
end ParityGen;
---------------------------------------------------------------------------
function ParityCheck(Val: Std_Logic_Vector; Parity: UX01)
return UX01 is
--Normalize the indexing
alias Data : Std_Logic_Vector(Val'length downto 1) is Val;
variable Result : UX01 := '1';
begin
for K in 1 to Data'length loop
Result := Result xor Data(K);
end loop;
return (Result xor Parity);
end ParityCheck;
---------------------------------------------------------------------------
function Decrement(Val : Std_Logic_Vector) return Std_Logic_Vector is
-- normalize the indexing
alias Input : Std_Logic_Vector(Val'length downto 1) is Val;
variable Result : Std_Logic_Vector(Input'range) := Input;
begin
for K in 1 to Input'length loop
Result(K) := not Input(K);
exit when Input(K) = '1';
end loop;
return Result;
end Decrement;
---------------------------------------------------------------------------
-- function Hex2Vec(HexInput: string; Width: positive)
-- return Std_Logic_Vector is
--
-- -- normalize the indexing
-- alias Hex : String(HexInput'length downto 1) is HexInput;
-- variable Temp : Std_Logic_Vector(HexInput'length*4 downto 0)
-- := (others => '0');
-- variable Result : Std_Logic_Vector(Width-1 downto 0)
-- := (others => '0');
-- variable J,K : natural;
-- begin
--
-- J := 0;
--
-- for K in 1 to HexInput'length loop
--
-- if not (Hex(K) = '_') then
--
-- case Hex(K) is
-- when '0' => Temp(J+3 downto J) := "0000";
--
-- when '1' => Temp(J+3 downto J) := "0001";
--
-- when '2' => Temp(J+3 downto J) := "0010";
--
-- when '3' => Temp(J+3 downto J) := "0011";
--
-- when '4' => Temp(J+3 downto J) := "0100";
--
-- when '5' => Temp(J+3 downto J) := "0101";
--
-- when '6' => Temp(J+3 downto J) := "0110";
--
-- when '7' => Temp(J+3 downto J) := "0111";
--
-- when '8' => Temp(J+3 downto J) := "1000";
--
-- when '9' => Temp(J+3 downto J) := "1001";
--
-- when 'a'|'A' => Temp(J+3 downto J) := "1010";
--
-- when 'b'|'B' => Temp(J+3 downto J) := "1011";
--
-- when 'c'|'C' => Temp(J+3 downto J) := "1100";
--
-- when 'd'|'D' => Temp(J+3 downto J) := "1101";
--
-- when 'e'|'E' => Temp(J+3 downto J) := "1110";
--
-- when 'f'|'F' => Temp(J+3 downto J) := "1111";
--
-- when others => Temp(J+3 downto J) := "XXXX";
-- end case;
--
-- J := J+4;
--
-- end if;
-- end loop;
--
-- Result := Temp(Width-1 downto 0);
-- return Result;
--
-- end Hex2Vec;
--
---------------------------------------------------------------------------
function Bool_To_UX01 (Val : Boolean) return UX01 is
begin
if Val then
return '1';
else
return '0';
end if;
end;
--------------------------------------------------------------------------------
function Vector_OR ( Data : Std_Logic_Vector ) return UX01 is
variable Result : UX01 := '0';
begin
for K in Data'low to Data'high loop
Result := Result or Data(K);
end loop;
return Result;
end;
---------------------------------------------------------------------------
function Compare (A,B : Std_Logic_Vector) return UX01 is
variable xor_vector : Std_Logic_Vector(A'Length downto 1);
variable result : UX01 := '0';
begin
-- assume that the length of A and B is equal
xor_vector := A xor B;
return Vector_OR (xor_vector);
end;
---------------------------------------------------------------------------
function ChkGen ( Data : in DataBits ) return CheckBits is
alias D31 : std_logic is Data(31);
alias D30 : std_logic is Data(30);
alias D29 : std_logic is Data(29);
alias D28 : std_logic is Data(28);
alias D27 : std_logic is Data(27);
alias D26 : std_logic is Data(26);
alias D25 : std_logic is Data(25);
alias D24 : std_logic is Data(24);
alias D23 : std_logic is Data(23);
alias D22 : std_logic is Data(22);
alias D21 : std_logic is Data(21);
alias D20 : std_logic is Data(20);
alias D19 : std_logic is Data(19);
alias D18 : std_logic is Data(18);
alias D17 : std_logic is Data(17);
alias D16 : std_logic is Data(16);
alias D15 : std_logic is Data(15);
alias D14 : std_logic is Data(14);
alias D13 : std_logic is Data(13);
alias D12 : std_logic is Data(12);
alias D11 : std_logic is Data(11);
alias D10 : std_logic is Data(10);
alias D09 : std_logic is Data(9);
alias D08 : std_logic is Data(8);
alias D07 : std_logic is Data(7);
alias D06 : std_logic is Data(6);
alias D05 : std_logic is Data(5);
alias D04 : std_logic is Data(4);
alias D03 : std_logic is Data(3);
alias D02 : std_logic is Data(2);
alias D01 : std_logic is Data(1);
alias D00 : std_logic is Data(0);
begin
return (
0 => D31 xor D30 xor D29 xor D28 xor D24 xor D21 xor D20 xor D19 xor
D15 xor D11 xor D10 xor D09 xor D08 xor D05 xor D04 xor D01,
1 => D30 xor D28 xor D25 xor D24 xor D20 xor D17 xor D16 xor D15 xor
D13 xor D12 xor D09 xor D08 xor D07 xor D06 xor D04 xor D03,
2 => not (D31 xor D26 xor D22 xor D19 xor D18 xor D16 xor D15 xor D14 xor
D10 xor D08 xor D06 xor D05 xor D04 xor D03 xor D02 xor D01),
3 => D31 xor D30 xor D27 xor D23 xor D22 xor D19 xor D15 xor D14 xor
D13 xor D12 xor D10 xor D09 xor D08 xor D07 xor D04 xor D00,
4 => not (D30 xor D29 xor D27 xor D26 xor D25 xor D24 xor D21 xor D19 xor
D17 xor D12 xor D10 xor D09 xor D04 xor D03 xor D02 xor D00),
5 => D31 xor D26 xor D25 xor D23 xor D21 xor D20 xor D18 xor D14 xor
D13 xor D11 xor D10 xor D09 xor D08 xor D06 xor D05 xor D00,
6 => D31 xor D30 xor D29 xor D28 xor D27 xor D23 xor D22 xor D19 xor
D18 xor D17 xor D16 xor D15 xor D11 xor D07 xor D02 xor D01 );
end;
---------------------------------------------------------------------------
---- 'ChkBits_In' are the checkbits read from the memory
---- 'Chk_Ok' are the checkbits generated from the data read from memory
---- 'Parity' is the parity read from the memory
function SyndromGenS ( ChkBits_In : CheckBits;
Chk_Ok : CheckBits;
Chk_Ok7 : std_logic;
Parity : std_logic ) return SyndromBits is
begin
-- One can generate a parity bit from the word instead of
-- using the generated checkbits as here
return (
7 => Chk_Ok7 xor Parity,
6 => Chk_Ok(6) xor Chkbits_In(6),
5 => Chk_Ok(5) xor Chkbits_In(5),
4 => Chk_Ok(4) xor Chkbits_In(4),
3 => Chk_Ok(3) xor Chkbits_In(3),
2 => Chk_Ok(2) xor Chkbits_In(2),
1 => Chk_Ok(1) xor Chkbits_In(1),
0 => Chk_Ok(0) xor Chkbits_In(0) );
end ;
function SyndromGen ( ChkBits_In : CheckBits;
Chk_Ok : CheckBits;
Parity : std_logic ) return SyndromBits is
begin
-- One can generate a parity bit from the word instead of
-- using the generated checkbits as here
return (
7 => Chk_Ok(6) xor Chk_Ok(5) xor not(Chk_Ok(4)) xor --gb 950527 bit 4 inverted
Chk_Ok(3) xor not(Chk_Ok(2)) xor Chk_Ok(1) xor --gb 950527 bit 4 inverted
Chk_Ok(0) xor Parity,
6 => Chk_Ok(6) xor Chkbits_In(6),
5 => Chk_Ok(5) xor Chkbits_In(5),
4 => Chk_Ok(4) xor Chkbits_In(4),
3 => Chk_Ok(3) xor Chkbits_In(3),
2 => Chk_Ok(2) xor Chkbits_In(2),
1 => Chk_Ok(1) xor Chkbits_In(1),
0 => Chk_Ok(0) xor Chkbits_In(0) );
end ;
-------------------------------------------------------------------------
function Correct_Data ( Syndrom : in SyndromBits;
Data : in Std_Logic_Vector ) return std_logic_vector is
begin
case Syndrom is
when "00111000" => return ( Data xor "000000000000000000000000000000001");
when "01000101" => return ( Data xor "000000000000000000000000000000010");
when "01010100" => return ( Data xor "000000000000000000000000000000100");
when "00010110" => return ( Data xor "000000000000000000000000000001000");
when "00011111" => return ( Data xor "000000000000000000000000000010000");
when "00100101" => return ( Data xor "000000000000000000000000000100000");
when "00100110" => return ( Data xor "000000000000000000000000001000000");
when "01001010" => return ( Data xor "000000000000000000000000010000000");
when "00101111" => return ( Data xor "000000000000000000000000100000000");
when "00111011" => return ( Data xor "000000000000000000000001000000000");
when "00111101" => return ( Data xor "000000000000000000000010000000000");
when "01100001" => return ( Data xor "000000000000000000000100000000000");
when "00011010" => return ( Data xor "000000000000000000001000000000000");
when "00101010" => return ( Data xor "000000000000000000010000000000000");
when "00101100" => return ( Data xor "000000000000000000100000000000000");
when "01001111" => return ( Data xor "000000000000000001000000000000000");
when "01000110" => return ( Data xor "000000000000000010000000000000000");
when "01010010" => return ( Data xor "000000000000000100000000000000000");
when "01100100" => return ( Data xor "000000000000001000000000000000000");
when "01011101" => return ( Data xor "000000000000010000000000000000000");
when "00100011" => return ( Data xor "000000000000100000000000000000000");
when "00110001" => return ( Data xor "000000000001000000000000000000000");
when "01001100" => return ( Data xor "000000000010000000000000000000000");
when "01101000" => return ( Data xor "000000000100000000000000000000000");
when "00010011" => return ( Data xor "000000001000000000000000000000000");
when "00110010" => return ( Data xor "000000010000000000000000000000000");
when "00110100" => return ( Data xor "000000100000000000000000000000000");
when "01011000" => return ( Data xor "000001000000000000000000000000000");
when "01000011" => return ( Data xor "000010000000000000000000000000000");
when "01010001" => return ( Data xor "000100000000000000000000000000000");
when "01011011" => return ( Data xor "001000000000000000000000000000000");
when "01101101" => return ( Data xor "010000000000000000000000000000000");
when "00000000" => return ( Data xor "100000000000000000000000000000000");
when "10000000" => return ( Data xor "000000000000000000000000000000000");
when others => if VecUnknown(syndrom) then
return "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
else
return data;
end if;
end case;
end Correct_Data;
------------------------------------------------------------------------
function NCError_Gen ( Syndrom : in SyndromBits ) return std_logic is
begin
case Syndrom is
when "00111000" | "01000101" | "01010100" | "00010110" | "00011111" | "00100101" |
"00100110" | "01001010" | "00101111" | "00111011" | "00111101" | "01100001" |
"00011010" | "00101010" | "00101100" | "01001111" | "01000110" | "01010010" |
"01100100" | "01011101" | "00100011" | "00110001" | "01001100" | "01101000" |
"00010011" | "00110010" | "00110100" | "01011000" | "01000011" | "01010001" |
"01011011" | "01101101" | "00000000" | "10000001" | "10000010" | "10000100" |
"10001000" | "10010000" | "10100000" | "11000000" | "10000000" => return '0';
when others => return '1';
end case;
end NCError_Gen;
----------------------------------------------------------------------
function CError_Gen ( Syndrom : in SyndromBits ) return std_logic is
begin
case Syndrom is
when "00111000" | "01000101" | "01010100" | "00010110" | "00011111" | "00100101" |
"00100110" | "01001010" | "00101111" | "00111011" | "00111101" | "01100001" |
"00011010" | "00101010" | "00101100" | "01001111" | "01000110" | "01010010" |
"01100100" | "01011101" | "00100011" | "00110001" | "01001100" | "01101000" |
"00010011" | "00110010" | "00110100" | "01011000" | "01000011" | "01010001" |
"01011011" | "01101101" | "00000000" | "10000001" | "10000010" | "10000100" |
"10001000" | "10010000" | "10100000" | "11000000" => return '1';
when others => return '0';
end case;
end CError_Gen;
end MECPackage;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: UART component
-- File name: uart.vhd
-- VHDL unit: uart
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned."+";
entity uart is
port(
MCK : in std_logic; -- Master clock provided
TBR1 : in std_logic; -- Transmitter Buffer Register (0)
TBR2 : in std_logic; -- Transmitter Buffer Register (1)
TBR3 : in std_logic; -- Transmitter Buffer Register (2)
TBR4 : in std_logic; -- Transmitter Buffer Register (3)
TBR5 : in std_logic; -- Transmitter Buffer Register (4)
TBR6 : in std_logic; -- Transmitter Buffer Register (5)
TBR7 : in std_logic; -- Transmitter Buffer Register (6)
TBR8 : in std_logic; -- Transmitter Buffer Register (7)
TBRL_N : in std_logic; -- Transmitter Buffer Register Load
CRL : in std_logic; -- Control Register Load
SBS : in std_logic; -- Stop Bit Select
PI : in std_logic; -- Parity Inhibit
EPE : in std_logic; -- Even Parity Enable (when PI is low)
DRR : in std_logic; -- Data Received Reset
TRC : in std_logic; -- Transmitter Register Clk
RRC : in std_logic; -- Receiver Register Clk
RRI : in std_logic; -- Receiver Register Input
MR : in std_logic; -- Master Reset
RBR1 : out std_logic; -- Receiver Buffer Register (0)
RBR2 : out std_logic; -- Receiver Buffer Register (1)
RBR3 : out std_logic; -- Receiver Buffer Register (2)
RBR4 : out std_logic; -- Receiver Buffer Register (3)
RBR5 : out std_logic; -- Receiver Buffer Register (4)
RBR6 : out std_logic; -- Receiver Buffer Register (5)
RBR7 : out std_logic; -- Receiver Buffer Register (6)
RBR8 : out std_logic; -- Receiver Buffer Register (7)
DR : out std_logic; -- Data Received
TBRE : out std_logic; -- Transmitter Buffer Register Empty
TRE : out std_logic; -- Transmitter Register Empty
FE : out std_logic; -- Frame Error
PE : out std_logic; -- Parity Error
OE : out std_logic; -- Overrun Error
TRO : out std_logic -- Transmitter Register Output
);
end uart;
architecture VHDL_RTL of uart is
constant ZD0 : std_logic_vector(3 downto 0) := "0000";
constant ZD1 : std_logic_vector(3 downto 0) := "0001";
constant ZD2 : std_logic_vector(3 downto 0) := "0010";
constant ZD3 : std_logic_vector(3 downto 0) := "0011";
constant ZD4 : std_logic_vector(3 downto 0) := "0100";
constant ZD5 : std_logic_vector(3 downto 0) := "0101";
constant ZD6 : std_logic_vector(3 downto 0) := "0110";
constant ZD7 : std_logic_vector(3 downto 0) := "0111";
constant ZD8 : std_logic_vector(3 downto 0) := "1000";
constant ZD9 : std_logic_vector(3 downto 0) := "1001";
constant ZD10 : std_logic_vector(3 downto 0) := "1010";
constant ZD11 : std_logic_vector(3 downto 0) := "1011";
constant ZD12 : std_logic_vector(3 downto 0) := "1100";
constant ZD13 : std_logic_vector(3 downto 0) := "1101";
constant ZD14 : std_logic_vector(3 downto 0) := "1110";
constant ZD15 : std_logic_vector(3 downto 0) := "1111";
-- programmation registers
signal PIReg : std_logic; -- Parity inhbit
signal EPEReg : std_logic; -- EvenParity Enable
signal SBSReg : std_logic; -- 2 Stop bits detected
-- Emission signals
signal SEmi : std_logic_Vector(3 downto 0); -- fsm state
signal Next_SEmi : std_logic_Vector(3 downto 0); -- next fsm state
signal CountClkEmi : std_logic_Vector(3 downto 0); -- counter used to divide TRC by 16
signal EnCountClkEmi : std_logic; -- Enable of the CountClkEmi counter
signal ZeroCountClkEmi : std_logic; -- CountClkEmi = 0000 and TRC enable
signal TransBufReg : std_logic_Vector(7 downto 0); -- temporary buffer register
signal TransmitReg : std_logic_Vector(9 downto 0); -- Transmit Register
signal LoadTransmitReg : std_logic; -- load Transmit Reg
signal ShiftTransmitReg : std_logic; -- shift Transmit Reg
signal EmiPar : std_logic; -- Emitted Parity
signal FlagTBRE : std_logic; -- A new Data is loaded in the Transmit
-- buffer register
signal SetFlagTBRE : std_logic; -- set Flag TBRE
signal TREActive : std_logic; -- active if fsm EMi in idle or end state
signal TREStopBit : std_logic; -- active during last Stop Bit
-- Reception Signals
signal RRI_R : std_logic; -- RRI after resynchro
signal SRec : std_logic_Vector(3 downto 0); -- fsm state
signal Next_SRec : std_logic_Vector(3 downto 0); -- next fsm state
signal CountClkRec : std_logic_Vector(3 downto 0); -- Reception Clk Counter
signal EnCountClkRec : std_logic; -- Enable rec Clk counting
signal DataBitSampled : std_logic; -- Active when a data bit is received
signal StartBitSampled : std_logic; -- Active when start bit is received
signal ParBitSampled : std_logic; -- Active when Parity bit is received
signal FirstStopBitSampled : std_logic; -- Active when 1st stop bit is received
signal SampleRec : std_logic; -- Active when data is sampled on RRI_R
signal ParecReg : std_logic; -- parity received register
signal PEReg : std_logic; -- Parity Error register
signal OEReg : std_logic; -- Overrun Error register
signal DRReg : std_logic; -- Data ready register
signal FEReg : std_logic; -- Frame Error register
signal ReceiveReg : std_logic_Vector(7 downto 0); -- receive register
signal RecBufReg : std_logic_Vector(7 downto 0); -- receive buffer register
begin
----------------------------------------------------------------------------
--These outputs are used inside, too.
TBRE <= FlagTBRE;
-- TRE is generated when emi fsm is idle
-- or during the second half of the last stop bit
--
TRE <= TREActive or ( TREStopBit and not(CountClkEmi(3)) ) ;
TRO <= TransmitReg(0);
RBR1 <= RecBufReg(0);
RBR2 <= RecBufReg(1);
RBR3 <= RecBufReg(2);
RBR4 <= RecBufReg(3);
RBR5 <= RecBufReg(4);
RBR6 <= RecBufReg(5);
RBR7 <= RecBufReg(6);
RBR8 <= RecBufReg(7);
FE <= FEReg;
OE <= OEReg;
DR <= DRReg;
PE <= PEReg;
----------------------------------------------------------------------------
-- Programming part
-- Synchronous Memorization of the parity, number of stop bits
-- upon receipt of the CRL signal compliant with the MCK clock
----------------------------------------------------------------------------
WriteControlRegister: process(MCK, MR)
begin
if (MR = '1') then
PIReg <= '0';
EPEReg <= '0';
SBSReg <= '0';
elsif (MCK'event and MCK = '1') then
-- when PI = 0 and EPE = 1 => parity EVEN
-- when PI = 0 and EPE = 0 => parity ODD
-- when PI = 1 and EPE = x => no parity, PE = 0
-- when SBS = 0 => 1 stop bit
-- when SBS = 1 => 2 stop bits
if CRL = '1' then
PIReg <= PI;
EPEReg <= EPE;
SBSReg <= SBS;
end if;
end if;
end process;
----------------------------------------------------------------------------
--Transmitting part
----------------------------------------------------------------------------
-- This counter is used to divide the TRC input by 16 to generate pulses on
-- TRO
-- It starts upon activation of EnCountClkEmi by the Emission fsm
-- It counts each time a TRC pulse is received
--
-- The ShiftTransmitReg shifts the transmission buffer in emission
-- one clock period after CountClkEmi = 0000 and TRC = '1'
--
TransmitClock: process(MCK, MR)
begin
if (MR = '1') then
CountClkEmi <= ZD15 ;
ShiftTransmitReg <= '0';
elsif (MCK'event and MCK = '1') then
if EnCountClkEmi = '0' then
CountClkEmi <= ZD15;
elsif EnCountClkEmi = '1' and TRC = '1' then
CountClkEmi <= CountClkEmi - 1;
end if;
ShiftTransmitReg <= ZeroCountClkEmi;
end if;
end process;
ZeroCountClkEmi <= '1' when CountClkEmi = ZD0 and TRC = '1' else '0';
----------------------------------------------------------------------------
-- Synchronous load of the transmit buffer register
-- on receipt of TBRL signal
-- A Flag is reset to indicate that the TB Register is not empty
--
WriteTransBufReg: process (MCK, MR)
begin
if (MR = '1') then
FlagTBRE <= '1';
TransBufReg <= "00000000";
elsif (MCK'event and MCK = '1') then
if TBRL_N = '0' then
TransBufReg(7) <= TBR8;
TransBufReg(6) <= TBR7;
TransBufReg(5) <= TBR6;
TransBufReg(4) <= TBR5;
TransBufReg(3) <= TBR4;
TransBufReg(2) <= TBR3;
TransBufReg(1) <= TBR2;
TransBufReg(0) <= TBR1;
FlagTBRE <= '0'; -- a new data to emit is received
end if;
if SetFlagTBRE = '1' then
FlagTBRE <= '1'; -- TB Register empty
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Synchronous load of the transmit register by the fsm
-- Start bit, parity and stop bit values are added
-- Synchronous shift of the register
--
-- There is a trick with the TransmitReg register
-- its size is only 10 bits ( 1 start bit + 8 data + parity )
-- the stop bit at 1 is generated by inputing 1
-- in bit 9 of the register !!
--
WriteTransReg: process (MCK, MR)
begin
if (MR = '1') then
TransmitReg <= "1111111111"; -- shall be set to 1
elsif (MCK'event and MCK = '1') then
if LoadTransmitReg = '1' then
TransmitReg(0) <= '0'; -- Start Bit
TransmitReg(1) <= TransBufReg(0); -- LSB
TransmitReg(2) <= TransBufReg(1);
TransmitReg(3) <= TransBufReg(2);
TransmitReg(4) <= TransBufReg(3);
TransmitReg(5) <= TransBufReg(4);
TransmitReg(6) <= TransBufReg(5);
TransmitReg(7) <= TransBufReg(6);
TransmitReg(8) <= TransBufReg(7); -- MSB
if PIReg = '1' then
TransmitReg(9) <= '1'; -- No parity (Stop Bit)
elsif EPEReg = '1' then
TransmitReg(9) <= EmiPar; -- Even Parity
else
TransmitReg(9) <= not EmiPar; -- Odd Parity
end if;
elsif ShiftTransmitReg = '1' then
TransmitReg(0) <= TransmitReg(1);
TransmitReg(1) <= TransmitReg(2);
TransmitReg(2) <= TransmitReg(3);
TransmitReg(3) <= TransmitReg(4);
TransmitReg(4) <= TransmitReg(5);
TransmitReg(5) <= TransmitReg(6);
TransmitReg(6) <= TransmitReg(7);
TransmitReg(7) <= TransmitReg(8);
TransmitReg(8) <= TransmitReg(9);
TransmitReg(9) <= '1'; -- furture stop bit
end if;
end if;
end process;
EmiPar <= TransBufReg(0) xor TransBufReg(1) xor TransBufReg(2) xor TransBufReg(3) xor
TransBufReg(4) xor TransBufReg(5) xor TransBufReg(6) xor TransBufReg(7);
----------------------------------------------------------------------------
-- Emission FSM
--
EMIfsm1 : process(MCK, MR)
begin
if(MR = '1') then
SEmi <= ZD0;
elsif (MCK'event and MCK = '1') then
SEmi <= Next_SEmi;
end if;
end process;
EMIfsm2 : process(SEmi, LoadTransmitReg, EnCountClkEmi, TRC,
SetFlagTBRE, SBSReg, PIReg, FlagTBRE,
ZeroCountClkEmi)
begin
Next_SEmi <= SEmi;
LoadTransmitReg <= '0';
EnCountClkEmi <= '0';
SetFlagTBRE <= '0';
TREActive <= '0';
TREStopBit <= '0';
case SEmi is
-- Idle State
when ZD0 =>
if FlagTBRE = '0' and TRC = '1' then
Next_SEmi <= ZD1;
end if;
TREActive <= '1'; -- Transmitted Register is empty
-- Load Transmit Register
-- Clear TRBL Flag
-- Emit Start Bit
when ZD1 =>
Next_SEmi <= ZD2;
LoadTransmitReg <= '1';
SetFlagTBRE <= '1';
EnCountClkEmi <= '1';
-- Continue to Emit Start Bit
-- (used since LoadTransmitReg shall last only 1 MCK period)
when ZD2 =>
if TRC = '1' then
Next_SEmi <= ZD3;
end if;
EnCountClkEmi <= '1';
-- Start Bit Emission
when ZD3 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD4;
end if;
EnCountClkEmi <= '1';
-- data bit emission 1
when ZD4 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD5;
end if;
EnCountClkEmi <= '1';
-- data bit emission 2
when ZD5 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD6;
end if;
EnCountClkEmi <= '1';
-- data bit emission 3
when ZD6 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD7;
end if;
EnCountClkEmi <= '1';
-- data bit emission 4
when ZD7 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD8;
end if;
EnCountClkEmi <= '1';
-- data bit emission 5
when ZD8 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD9;
end if;
EnCountClkEmi <= '1';
-- data bit emission 6
when ZD9 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD10;
end if;
EnCountClkEmi <= '1';
-- data bit emission 7
when ZD10 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD11;
end if;
EnCountClkEmi <= '1';
-- data bit emission 8
when ZD11 =>
if ZeroCountClkEmi = '1' then
if PIReg = '1' then
if SBSReg = '0' then
Next_SEmi <= ZD14; -- no parity 1 stop bit jump to last stop bit
else
Next_SEmi <= ZD13; -- no parity 2 stop bits
end if;
else
Next_SEmi <= ZD12; -- parity
end if;
end if;
EnCountClkEmi <= '1';
-- parity
when ZD12 =>
if ZeroCountClkEmi = '1' then
if SBSreg = '0' then
Next_SEmi <= ZD14; -- 1 stop bit jump to last stop bit
else
Next_SEmi <= ZD13; -- 2 stop bits
end if;
end if;
EnCountClkEmi <= '1';
-- first stop bit in case of 2 stop bits
when ZD13 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD14; -- 2 stop bits
end if;
EnCountClkEmi <= '1';
-- 2nd stop bit or 1st stop bit if only 1
when ZD14 =>
if ZeroCountClkEmi = '1' then
Next_SEmi <= ZD15;
end if;
TREStopBit <= '1'; -- TRE is generated in this period
EnCountClkEmi <= '1';
-- end state
--
when ZD15 =>
if FlagTBRE = '0' then
Next_SEmi <= ZD2;
LoadTransmitReg <= '1';
SetFlagTBRE <= '1';
EnCountClkEmi <= '1';
else
Next_SEmi <= ZD0;
end if;
TREActive <= '1'; -- Transmitted Register is empty
when others =>
Next_SEmi <= ZD0;
end case;
end process;
----------------------------------------------------------------------------
--RECEIVING PART
----------------------------------------------------------------------------
-- this counter is used to synchronize the data In sample w.r.t. the
-- receive clock RRC
-- The data is sampled when the counter is 0111 and RRC = 1
-- Resynchronization of RRI_R
--
ReceiveClk: process(MCK, MR)
begin
if (MR = '1') then
CountClkRec <= "0000";
RRI_R <= '1';
elsif (MCK'event and MCK = '1') then
if (EnCountClkRec = '0') then
CountClkRec <= "0000";
elsif EnCountClkRec = '1' and RRC = '1' then
CountClkRec <= CountClkRec + 1;
end if;
RRI_R <= RRI;
end if;
end process;
ReceiveClk1: process(CountClkRec, RRC)
begin
if RRC = '1' and CountClkRec = "0111" then
SampleRec <= '1';
else
SampleRec <= '0';
end if;
end process;
----------------------------------------------------------------------------
-- finite state for the receive part
-- this fsm starts upon receipt of a start bit
--
----------------------------------------------------------------------------
-- Emission FSM
--
RECfsm1 : process(MCK, MR)
begin
if(MR = '1') then
SRec <= ZD0;
elsif (MCK'event and MCK = '1') then
SRec <= Next_SRec;
end if;
end process;
RECfsm2: process(SRec, SampleRec, RRI_R,
PIReg, SBSReg, EPEReg)
begin
EnCountClkRec <= '0';
DataBitSampled <= '0';
StartBitSampled <= '0';
ParBitSampled <= '0';
FirstStopBitSampled <= '0';
Next_SRec <= Srec;
case SRec is
-- idle State
-- waiting for start bit
when ZD0 =>
if RRI_R = '0' then
Next_SRec <= ZD1;
end if;
-- start Counting
-- falling edge detected on RRI_R
-- and wait for middle of start bit
when ZD1 =>
if SampleRec = '1' then
if RRI_R = '0' then
Next_SRec <= ZD2; -- ok start bit sampled at 0
else
Next_SRec <= ZD0; -- wrong start bit
end if;
StartBitSampled <= '1'; -- init parity computation
end if;
EnCountClkRec <= '1';
-- to middle of data bit 1
when ZD2 =>
if SampleRec = '1' then
Next_SRec <= ZD3;
DataBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of data bit 2
when ZD3 =>
if SampleRec = '1' then
Next_SRec <= ZD4;
DataBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of data bit 3
when ZD4 =>
if SampleRec = '1' then
Next_SRec <= ZD5;
DataBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of data bit 4
when ZD5 =>
if SampleRec = '1' then
Next_SRec <= ZD6;
DataBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of data bit 5
when ZD6 =>
if SampleRec = '1' then
Next_SRec <= ZD7;
DataBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of data bit 6
when ZD7 =>
if SampleRec = '1' then
Next_SRec <= ZD8;
DataBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of data bit 7
when ZD8 =>
if SampleRec = '1' then
Next_SRec <= ZD9;
DataBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of data bit 8
when ZD9 =>
if SampleRec = '1' then
if PIReg = '1' then
Next_SRec <= ZD11; -- no parity -> 1st stop bit
else
Next_SRec <= ZD10; -- parity
end if;
DataBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of parity bit if any
when ZD10 =>
if SampleRec = '1' then
Next_SRec <= ZD11; -- 1 st stop bit
ParBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of first stop bit
when ZD11 =>
if SampleRec = '1' then
if SBSReg = '1' then
Next_SRec <= ZD12; -- second stop bit
else
Next_SRec <= ZD13; -- only 1 stop bit
end if;
FirstStopBitSampled <= '1';
end if;
EnCountClkRec <= '1';
-- to middle of the second stop bit (if 2 stop bits)
when ZD12 =>
if SampleRec = '1' then
Next_SRec <= ZD13;
end if;
EnCountClkRec <= '1';
-- end
when ZD13 =>
-- return to ZD0 only if a level 1 was detected
if RRI_R = '1' then
Next_Srec <= ZD0; -- TBC
end if;
when others =>
Next_Srec <= ZD0;
end case;
end process;
----------------------------------------------------------------------------
-- Receive Shift Register
-- The register is shifted at each sample
--
RecRegProc : process(MCK, MR)
begin
if (MR = '1') then
ReceiveReg <= "00000000";
elsif (MCK'event and MCK = '1') then
if DataBitSampled = '1' then
ReceiveReg(0) <= ReceiveReg(1);
ReceiveReg(1) <= ReceiveReg(2);
ReceiveReg(2) <= ReceiveReg(3);
ReceiveReg(3) <= ReceiveReg(4);
ReceiveReg(4) <= ReceiveReg(5);
ReceiveReg(5) <= ReceiveReg(6);
ReceiveReg(6) <= ReceiveReg(7);
ReceiveReg(7) <= RRI_R;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Receive Buffer Register
-- This register is loaded by the fsm during the first stop bit
--
ReceiveProc: process(MCK, MR)
begin
if (MR = '1') then
RecBufReg <= "00000000";
elsif (MCK'event and MCK = '1') then
if FirstStopBitSampled = '1' then
RecBufReg <= ReceiveReg;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- This process manages the Parity for the receive part
-- when the receiving process starts the ParecReg is set to 1 or 0 depending
-- on the parity to compute
-- Then for each data bit received parity is computed and memorized
-- When the parity bit is received it is compared to the ParecReg regiter (parity ODD/EVEN)
-- if the result is false it is set to 1.
-- The value of this register is loaded in PEReg at the same time as RBR reg
--
ParityCompute: process(MCK, MR)
begin
if (MR = '1') then
ParecReg <= '0';
elsif (MCK'event and MCK = '1') then
if StartBitSampled = '1' then -- initialise parity computation
ParecReg <= not EPEReg; -- 0 for Even Parity 1 for Odd parity
elsif DataBitSampled = '1' then -- compute parity
ParecReg <= ParecReg xor RRI_R;
elsif ParBitSampled = '1' then -- test parity
if Parecreg = RRI_R then
ParecReg <= '0'; -- Parity good
else
ParecReg <= '1'; -- Parity wrong
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Computation of the Frame Error Error, Parity Error
-- Frame Errot is Active if the first stop bit is not at 1
--
FEprocess: process(MCK, MR)
begin
if (MR = '1') then
FEReg <= '0';
PEReg <= '0';
elsif (MCK'event and MCK = '1') then
-- NOTE : TO BE CORRECTED DR and FE shall be generated later
if FirstStopBitSampled = '1' then
if RRI_R = '0' then
--rc FEReg <= '1'; -- error first stop bit is zero
FEReg <= '1' or FEReg; -- error first stop bit is zero
else
FEReg <= '0'; -- no error
end if;
if PIReg = '1' then
PEReg <= '0'; -- no parity => no parity error
else
--rc PEReg <= Parecreg;
PEReg <= Parecreg or PEReg; -- hold the error until MR activation
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Data ready and Overrun Error management
-- Data Ready is cleared by the DRR signal and set when data is transferred (1st stop bit)
-- Overrun error is set to 1 if DRreg is active when First Stop Bit
OEProcess: process(MCK, MR)
begin
if (MR = '1') then
DRReg <= '0';
OEReg <= '0';
elsif (MCK'event and MCK = '1') then
if DRR = '0' then
DRReg <= '0'; -- DR clear on DRR high
elsif FirstStopBitSampled = '1' then
DRReg <= '1';
end if;
-- NOTE : TO BE CORRECTED DR and FE shall be generated later
if FirstStopBitSampled = '1' then
if DRReg = '1' then
OEReg <= '1'; -- OE error
else
OEReg <= '0';
end if;
end if;
end if;
end process;
end VHDL_RTL;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: UART control
-- File name: \mec\source\uartctl.vhd
-- VHDL unit: UARTControl
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UARTControl is
port (
Clk_Int : in Std_Logic;
Reset_Int_N : in Std_Logic;
DoNotRdUART : in Std_Logic;
GUARTAReg_N : in Std_Logic;
GUARTBReg_N : in Std_Logic;
GUARTStatusReg_N : in Std_Logic;
UARTAReg_N : in Std_Logic;
UARTBReg_N : in Std_Logic;
UARTStatusReg_N : in Std_Logic;
MECControlReg_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
Rd_Int_In : in Std_Logic;
D_Int_In : in Std_Logic_Vector(31 downto 0);
Intr_UARTA_Data : out Std_Logic;
Intr_UARTB_Data : out Std_Logic;
UARTs_Quiet : out Std_Logic;
Intr_UART_Err : out Std_Logic;
D_UARTA_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTA_Out : out Std_Logic;
D_UARTB_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTB_Out : out Std_Logic;
D_UARTS_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTS_Out : out Std_Logic;
D_Ready_A : in Std_Logic;
D_Ready_B : in Std_Logic;
O_Err_A : in Std_Logic;
O_Err_B : in Std_Logic;
Frame_Err_A : in Std_Logic;
Frame_Err_B : in Std_Logic;
Par_Err_A : in Std_Logic;
Par_Err_B : in Std_Logic;
TrHoRegEm_A : in Std_Logic;
TrHoRegEm_B : in Std_Logic;
TrSeRegEm_A : in Std_Logic;
TrSeRegEm_B : in Std_Logic;
D_UART_A_Out : in Std_Logic_Vector(7 downto 0);
D_UART_B_Out : in Std_Logic_Vector(7 downto 0);
MReset_A : out Std_Logic;
MReset_B : out Std_Logic;
D_ReadyRes_A_N : out Std_Logic;
D_ReadyRes_B_N : out Std_Logic;
Wr_Data_A_N : out Std_Logic;
Wr_Data_B_N : out Std_Logic;
Wr_Control : out Std_Logic;
SBSel : out Std_Logic;
EvenOdd_N : out Std_Logic;
ParInh : out Std_Logic;
D_UART_In : out Std_Logic_Vector(7 downto 0)
);
end UARTControl;
architecture Mini_Spec of UARTControl is
signal UART_A_Reg1 : Std_Logic_Vector(7 downto 0);
signal UART_A_Par1 : Std_Logic;
signal UART_B_Reg1 : Std_Logic_Vector(7 downto 0);
signal UART_B_Par1 : Std_Logic;
signal UART_Status_Reg1 : Std_Logic_Vector(23 downto 0);
signal UART_Status_Par1 : Std_Logic;
signal UART_A_Reg : Std_Logic_Vector(7 downto 0);
signal UART_A_Par : Std_Logic;
signal UART_B_Reg : Std_Logic_Vector(7 downto 0);
signal UART_B_Par : Std_Logic;
signal UART_Status_Reg : Std_Logic_Vector(23 downto 0);
signal UART_Status_Par : Std_Logic;
signal TrSeRegEm_A_rck : Std_Logic;
signal TrSeRegEm_B_rck : Std_Logic;
signal TrSeRegEm_A_redge : Std_Logic;
signal TrSeRegEm_B_redge : Std_Logic;
signal D_Ready_A_rck : Std_Logic;
signal D_Ready_B_rck : Std_Logic;
signal D_Ready_A_redge : Std_Logic;
signal D_Ready_B_redge : Std_Logic;
signal Intr_UART_Err_rck : Std_Logic;
signal D7 : Std_Logic;
signal D23 : Std_Logic;
begin
----------------------------------------------------------------------------
Data_Hold: process
begin
wait until Clk_Int'event and Clk_Int = '0';
D7 <= D_Int_In(7);
D23 <= D_Int_In(23);
D_UART_In <= D_Int_In(7 downto 0);
ParInh <= not D_Int_In(20);
EvenOdd_N <= not D_Int_In(21);
SBSel <= D_Int_In(22);
end process;
----------------------------------------------------------------------------
UARTs_Quiet <= TrHoRegEm_A and TrHoRegEm_B and TrSeRegEm_A and TrSeRegEm_B;
----------------------------------------------------------------------------
Sync_Intr_UART: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N ='0' then
TrSeRegEm_A_rck <= '1';
D_Ready_A_rck <= '0';
TrSeRegEm_B_rck <= '1';
D_Ready_B_rck <= '0';
Intr_UART_Err_rck <= '1';
elsif Clk_Int'event and Clk_Int = '1' then
TrSeRegEm_A_rck <= TrSeRegEm_A;
D_Ready_A_rck <= D_Ready_A;
TrSeRegEm_B_rck <= TrSeRegEm_B;
D_Ready_B_rck <= D_Ready_B;
Intr_UART_Err_rck <= O_Err_A or Par_Err_A or Frame_Err_A or
O_Err_B or Par_Err_B or Frame_Err_B;
end if;
end process;
TrSeRegEm_A_redge <= TrSeRegEm_A and not(TrSeRegEm_A_rck);
TrSeRegEm_B_redge <= TrSeRegEm_B and not(TrSeRegEm_B_rck);
D_Ready_A_redge <= D_Ready_A and not(D_Ready_A_rck);
D_Ready_B_redge <= D_Ready_B and not(D_Ready_B_rck);
Intr_UARTA_Data <= (D_Ready_A_redge or TrSeRegEm_A_redge) and
not(Frame_Err_A or Par_Err_A or O_Err_A);
Intr_UARTB_Data <= (D_Ready_B_redge or TrSeRegEm_B_redge) and
not(Frame_Err_B or Par_Err_B or O_Err_B);
Intr_UART_Err <= (O_Err_A or Par_Err_A or Frame_Err_A or
O_Err_B or Par_Err_B or Frame_Err_B) and not Intr_UART_Err_rck;
----------------------------------------------------------------------------
-- MReset high for 2 Clk period, It is used by the UARTs as
-- an asynchronous reset
-- The UARTs are working on the rising edge so the
-- aynchronous reset is generated on ck+
MasterReset: process(Reset_Int_N, Clk_Int)
type states is (S0, S1);
variable state :states;
begin
if Reset_Int_N = '0' then
MReset_A <= '1';
MReset_B <= '1';
state := S1;
elsif Clk_Int'event and Clk_Int='1' then
case state is
when S0 => if (UARTStatusReg_N = '0') and (Wr_Int_N = '0') then
MReset_A <= D7;
MReset_B <= D23;
state := S1;
else
MReset_A <= '0';
MReset_B <= '0';
state := S0;
end if;
when S1 => state:=S0;
end case;
end if;
end process;
----------------------------------------------------------------------------
DataReadyReset: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N = '0' then
D_ReadyRes_A_N <= '1';
D_ReadyRes_B_N <= '1';
elsif Clk_Int'event and Clk_Int = '1' then
if Rd_Int_In = '1' and DoNotRdUART = '0' and
GUARTAReg_N = '0' and D_Ready_A = '1' then
D_ReadyRes_A_N <= '0';
D_ReadyRes_B_N <= '1';
elsif Rd_Int_In = '1' and DoNotRdUART = '0' and
GUARTBReg_N = '0' and D_Ready_B = '1' then
D_ReadyRes_A_N <= '1';
D_ReadyRes_B_N <= '0';
else
D_ReadyRes_A_N <= '1';
D_ReadyRes_B_N <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------
WriteStrobes: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N = '0' then
Wr_Data_A_N <= '1';
Wr_Data_B_N <= '1';
Wr_Control <= '0';
elsif Clk_Int'event and Clk_Int='0' then
Wr_Data_A_N <= Wr_Int_N or UARTAReg_N;
Wr_Data_B_N <= Wr_Int_N or UARTBReg_N;
Wr_Control <= not (Wr_Int_N or MECControlReg_N);
end if;
end process;
----------------------------------------------------------------------------
-- Sample signals for UART A RX/TX Register
UART_A_Reg1(7 downto 0) <= D_UART_A_Out;
-- UART_A_Reg1(8) <= D_Ready_A and not(Frame_Err_A or Par_Err_A or O_Err_A);
-- UART_A_Reg1(9) <= TrSeRegEm_A;
-- UART_A_Reg1(10) <= TrHoRegEm_A;
UART_A_Par1 <= ParityGen(UART_A_Reg1);
-- Sample signals for UART B RX/TX Register
UART_B_Reg1(7 downto 0) <= D_UART_B_Out;
-- UART_B_Reg1(8) <= D_Ready_B and not(Frame_Err_B or Par_Err_B or O_Err_B);
-- UART_B_Reg1(9) <= TrSeRegEm_B;
-- UART_B_Reg1(10) <= TrHoRegEm_B;
UART_B_Par1 <= ParityGen(UART_B_Reg1);
-- Sample signals for UART Status Register
UART_Status_Reg1(0) <= D_Ready_A and not(Frame_Err_A or Par_Err_A or O_Err_A);
UART_Status_Reg1(1) <= TrSeRegEm_A;
UART_Status_Reg1(2) <= TrHoRegEm_A;
UART_Status_Reg1(3) <= '0';
UART_Status_Reg1(4) <= Frame_Err_A;
UART_Status_Reg1(5) <= Par_Err_A;
UART_Status_Reg1(6) <= O_Err_A;
UART_Status_Reg1(15 downto 7)<= "000000000";
UART_Status_Reg1(16) <= D_Ready_B and not(Frame_Err_B or Par_Err_B or O_Err_B);
UART_Status_Reg1(17) <= TrSeRegEm_B;
UART_Status_Reg1(18) <= TrHoRegEm_B;
UART_Status_Reg1(19) <= '0';
UART_Status_Reg1(20) <= Frame_Err_B;
UART_Status_Reg1(21) <= Par_Err_B;
UART_Status_Reg1(22) <= O_Err_B;
UART_Status_Reg1(23) <= '0';
UART_Status_Par1 <= ParityGen(UART_Status_Reg1);
DataSampleProc1: process(Clk_Int)
begin
if Clk_Int'event and Clk_Int = '1' then
if Rd_Int_In = '1' and GUARTAReg_N = '0' then
UART_A_Reg <= UART_A_Reg;
UART_A_Par <= UART_A_Par;
else
UART_A_Reg <= UART_A_Reg1;
UART_A_Par <= UART_A_Par1;
end if;
end if;
end process;
DataSampleProc2: process(Clk_Int)
begin
if Clk_Int'event and Clk_Int = '1' then
if Rd_Int_In = '1' and GUARTBReg_N = '0' then
UART_B_Reg <= UART_B_Reg;
UART_B_Par <= UART_B_Par;
else
UART_B_Reg <= UART_B_Reg1;
UART_B_Par <= UART_B_Par1;
end if;
end if;
end process;
DataSampleProc3: process(Clk_Int)
begin
if Clk_Int'event and Clk_Int = '1' then
if Rd_Int_In = '1' and GUARTStatusReg_N = '0' then
UART_Status_Reg(6 downto 0) <= UART_Status_Reg(6 downto 0);
UART_Status_Reg(22 downto 16) <= UART_Status_Reg(22 downto 16);
UART_Status_Par <= UART_Status_Par;
else
UART_Status_Reg(6 downto 0) <= UART_Status_Reg1(6 downto 0);
UART_Status_Reg(22 downto 16) <= UART_Status_Reg1(22 downto 16);
UART_Status_Par <= UART_Status_Par1;
end if;
end if;
end process;
process(UART_A_Reg,UART_A_Par,UART_B_Reg,UART_B_Par,
UART_Status_Reg,UART_Status_Par)
begin
D_UARTA_Out(7 downto 0) <= UART_A_Reg;
D_UARTA_Out(31 downto 8) <= "000000000000000000000000";
DPar_UARTA_Out <= UART_A_Par;
D_UARTB_Out(7 downto 0) <= UART_B_Reg;
D_UARTB_Out(31 downto 8) <= "000000000000000000000000";
DPar_UARTB_Out <= UART_B_Par;
D_UARTS_Out(6 downto 0) <= UART_Status_Reg(6 downto 0);
D_UARTS_Out(15 downto 7) <= "000000000";
D_UARTS_Out(22 downto 16) <= UART_Status_Reg(22 downto 16);
D_UARTS_Out(31 downto 23) <= "000000000";
DPar_UARTS_Out <= UART_Status_Par;
end process;
end Mini_Spec ;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: UART control
-- File name: \mec\source\uarts.vhd
-- VHDL unit: UARTs
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
entity UARTs is
port (
Clk_Int : in Std_Logic;
UART_Clk_En : in Std_Logic;
Reset_Int_N : in Std_Logic;
DoNotRdUART : in Std_Logic;
GUARTAReg_N : in Std_Logic;
GUARTBReg_N : in Std_Logic;
GUARTStatusReg_N : in Std_Logic;
UARTAReg_N : in Std_Logic;
UARTBReg_N : in Std_Logic;
UARTStatusReg_N : in Std_Logic;
MECControlReg_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
Rd_Int_In : in Std_Logic;
D_Int_In : in Std_Logic_Vector(31 downto 0);
RxA_In : in Std_Logic;
RxB_In : in Std_Logic;
TxA_Out : out Std_Logic;
TxB_Out : out Std_Logic;
Intr_UARTA_Data : out Std_Logic;
Intr_UARTB_Data : out Std_Logic;
UARTs_Quiet : out Std_Logic;
Intr_UART_Err : out Std_Logic;
D_UARTA_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTA_Out : out Std_Logic;
D_UARTB_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTB_Out : out Std_Logic;
D_UARTS_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTS_Out : out Std_Logic
);
end UARTs;
architecture Mini_spec of UARTs is
component UART
port (
MCK : in std_logic; -- MEC clock
TBR1 : in Std_Logic; -- D_UART_In(0)
TBR2 : in Std_Logic; -- D_UART_In(1)
TBR3 : in Std_Logic; -- D_UART_In(2)
TBR4 : in Std_Logic; -- D_UART_In(3)
TBR5 : in Std_Logic; -- D_UART_In(4)
TBR6 : in Std_Logic; -- D_UART_In(5)
TBR7 : in Std_Logic; -- D_UART_In(6)
TBR8 : in Std_Logic; -- D_UART_In(7)
TBRL_N : in Std_Logic; -- Wr_Data_N
CRL : in Std_Logic; -- Wr_Control
SBS : in Std_Logic; -- SBSel
PI : in Std_Logic; -- ParInh
EPE : in Std_Logic; -- EvenOdd_N
DRR : in Std_Logic; -- D_ReadyRes_N
TRC : in Std_Logic; -- UART_Clk_En_T
RRC : in Std_Logic; -- UART_Clk_En_R
RRI : in Std_Logic; -- Rx_In
MR : in Std_Logic; -- MReset
RBR1 : out Std_Logic; -- D_UART_Out(0)
RBR2 : out Std_Logic; -- D_UART_Out(1)
RBR3 : out Std_Logic; -- D_UART_Out(2)
RBR4 : out Std_Logic; -- D_UART_Out(3)
RBR5 : out Std_Logic; -- D_UART_Out(4)
RBR6 : out Std_Logic; -- D_UART_Out(5)
RBR7 : out Std_Logic; -- D_UART_Out(6)
RBR8 : out Std_Logic; -- D_UART_Out(7)
DR : out Std_Logic; -- D_Ready
TBRE : out Std_Logic; -- TrHoRegEm
TRE : out Std_Logic; -- TrSeRegEm
FE : out Std_Logic; -- Frame_Err
PE : out Std_Logic; -- Par_Err
OE : out Std_Logic; -- O_Err
TRO : out Std_Logic -- Tx_Out
);
end component;
component UARTControl
port (
Clk_Int : in Std_Logic;
Reset_Int_N : in Std_Logic;
DoNotRdUART : in Std_Logic;
GUARTAReg_N : in Std_Logic;
GUARTBReg_N : in Std_Logic;
GUARTStatusReg_N : in Std_Logic;
UARTAReg_N : in Std_Logic;
UARTBReg_N : in Std_Logic;
UARTStatusReg_N : in Std_Logic;
MECControlReg_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
Rd_Int_In : in Std_Logic;
D_Int_In : in Std_Logic_Vector(31 downto 0);
Intr_UARTA_Data : out Std_Logic;
Intr_UARTB_Data : out Std_Logic;
UARTs_Quiet : out Std_Logic;
Intr_UART_Err : out Std_Logic;
D_UARTA_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTA_Out : out Std_Logic;
D_UARTB_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTB_Out : out Std_Logic;
D_UARTS_Out : out Std_Logic_Vector(31 downto 0);
DPar_UARTS_Out : out Std_Logic;
D_Ready_A : in Std_Logic;
D_Ready_B : in Std_Logic;
O_Err_A : in Std_Logic;
O_Err_B : in Std_Logic;
Frame_Err_A : in Std_Logic;
Frame_Err_B : in Std_Logic;
Par_Err_A : in Std_Logic;
Par_Err_B : in Std_Logic;
TrHoRegEm_A : in Std_Logic;
TrHoRegEm_B : in Std_Logic;
TrSeRegEm_A : in Std_Logic;
TrSeRegEm_B : in Std_Logic;
D_UART_A_Out : in Std_Logic_Vector(7 downto 0);
D_UART_B_Out : in Std_Logic_Vector(7 downto 0);
MReset_A : out Std_Logic;
MReset_B : out Std_Logic;
D_ReadyRes_A_N: out Std_Logic;
D_ReadyRes_B_N: out Std_Logic;
Wr_Data_A_N : out Std_Logic;
Wr_Data_B_N : out Std_Logic;
Wr_Control : out Std_Logic;
SBSel : out Std_Logic;
EvenOdd_N : out Std_Logic;
ParInh : out Std_Logic;
D_UART_In : out Std_Logic_Vector(7 downto 0)
);
end component;
signal D_Ready_A : Std_Logic;
signal D_Ready_B : Std_Logic;
signal O_Err_A : Std_Logic;
signal O_Err_B : Std_Logic;
signal Frame_Err_A : Std_Logic;
signal Frame_Err_B : Std_Logic;
signal Par_Err_A : Std_Logic;
signal Par_Err_B : Std_Logic;
signal TrHoRegEm_A : Std_Logic;
signal TrHoRegEm_B : Std_Logic;
signal TrSeRegEm_A : Std_Logic;
signal TrSeRegEm_B : Std_Logic;
signal D_UART_A_Out : Std_Logic_Vector(7 downto 0);
signal D_UART_B_Out : Std_Logic_Vector(7 downto 0);
signal MReset_A : Std_Logic;
signal MReset_B : Std_Logic;
signal D_ReadyRes_A_N : Std_Logic;
signal D_ReadyRes_B_N : Std_Logic;
signal Wr_Data_A_N : Std_Logic;
signal Wr_Data_B_N : Std_Logic;
signal Wr_Control : Std_Logic;
signal SBSel : Std_Logic;
signal EvenOdd_N : Std_Logic;
signal ParInh : Std_Logic;
signal D_UART_In : Std_Logic_Vector(7 downto 0);
signal TxA : Std_logic;
signal TxB : Std_logic;
begin
TxA_Out <= TxA;
TxB_Out <= TxB;
UARTControl_1 : UARTControl
port map (
Clk_Int => Clk_Int,
Reset_Int_N => Reset_Int_N,
DoNotRdUART => DoNotRdUART,
GUARTAReg_N => GUARTAReg_N,
GUARTBReg_N => GUARTBReg_N,
GUARTStatusReg_N => GUARTStatusReg_N,
UARTAReg_N => UARTAReg_N,
UARTBReg_N => UARTBReg_N,
UARTStatusReg_N => UARTStatusReg_N,
MECControlReg_N => MECControlReg_N,
Wr_Int_N => Wr_Int_N,
Rd_Int_In => Rd_Int_In,
D_Int_In => D_Int_In,
Intr_UARTA_Data => Intr_UARTA_Data,
Intr_UARTB_Data => Intr_UARTB_Data,
UARTs_Quiet => UARTs_Quiet,
Intr_UART_Err => Intr_UART_Err,
D_UARTA_Out => D_UARTA_Out,
DPar_UARTA_Out => DPar_UARTA_Out,
D_UARTB_Out => D_UARTB_Out,
DPar_UARTB_Out => DPar_UARTB_Out,
D_UARTS_Out => D_UARTS_Out,
DPar_UARTS_Out => DPar_UARTS_Out,
D_Ready_A => D_Ready_A,
D_Ready_B => D_Ready_B,
O_Err_A => O_Err_A,
O_Err_B => O_Err_B,
Frame_Err_A => Frame_Err_A,
Frame_Err_B => Frame_Err_B,
Par_Err_A => Par_Err_A,
Par_Err_B => Par_Err_B,
TrHoRegEm_A => TrHoRegEm_A,
TrHoRegEm_B => TrHoRegEm_B,
TrSeRegEm_A => TrSeRegEm_A,
TrSeRegEm_B => TrSeRegEm_B,
D_UART_A_Out => D_UART_A_Out,
D_UART_B_Out => D_UART_B_Out,
MReset_A => MReset_A,
MReset_B => MReset_B,
D_ReadyRes_A_N => D_ReadyRes_A_N,
D_ReadyRes_B_N => D_ReadyRes_B_N,
Wr_Data_A_N => Wr_Data_A_N,
Wr_Data_B_N => Wr_Data_B_N,
Wr_Control => Wr_Control,
SBSel => SBSel,
EvenOdd_N => EvenOdd_N,
ParInh => ParInh,
D_UART_In => D_UART_In
);
UART_A : UART
port map (
MCK => Clk_Int,
TBR1 => D_UART_In(0),
TBR2 => D_UART_In(1),
TBR3 => D_UART_In(2),
TBR4 => D_UART_In(3),
TBR5 => D_UART_In(4),
TBR6 => D_UART_In(5),
TBR7 => D_UART_In(6),
TBR8 => D_UART_In(7),
TBRL_N => Wr_Data_A_N,
CRL => Wr_Control,
SBS => SBSel,
PI => ParInh,
EPE => EvenOdd_N,
DRR => D_ReadyRes_A_N,
TRC => UART_Clk_En,
RRC => UART_Clk_En,
RRI => RxA_In,
MR => MReset_A,
RBR1 => D_UART_A_Out(0),
RBR2 => D_UART_A_Out(1),
RBR3 => D_UART_A_Out(2),
RBR4 => D_UART_A_Out(3),
RBR5 => D_UART_A_Out(4),
RBR6 => D_UART_A_Out(5),
RBR7 => D_UART_A_Out(6),
RBR8 => D_UART_A_Out(7),
DR => D_Ready_A,
TBRE => TrHoRegEm_A,
TRE => TrSeRegEm_A,
FE => Frame_Err_A,
PE => Par_Err_A,
OE => O_Err_A,
TRO => TxA
);
UART_B : UART
port map (
MCK => Clk_Int,
TBR1 => D_UART_In(0),
TBR2 => D_UART_In(1),
TBR3 => D_UART_In(2),
TBR4 => D_UART_In(3),
TBR5 => D_UART_In(4),
TBR6 => D_UART_In(5),
TBR7 => D_UART_In(6),
TBR8 => D_UART_In(7),
TBRL_N => Wr_Data_B_N,
CRL => Wr_Control,
SBS => SBSel,
PI => ParInh,
EPE => EvenOdd_N,
DRR => D_ReadyRes_B_N,
TRC => UART_Clk_En,
RRC => UART_Clk_En,
RRI => RxB_In,
MR => MReset_B,
RBR1 => D_UART_B_Out(0),
RBR2 => D_UART_B_Out(1),
RBR3 => D_UART_B_Out(2),
RBR4 => D_UART_B_Out(3),
RBR5 => D_UART_B_Out(4),
RBR6 => D_UART_B_Out(5),
RBR7 => D_UART_B_Out(6),
RBR8 => D_UART_B_Out(7),
DR => D_Ready_B,
TBRE => TrHoRegEm_B,
TRE => TrSeRegEm_B,
FE => Frame_Err_B,
PE => Par_Err_B,
OE => O_Err_B,
TRO => TxB );
end Mini_Spec;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: general purpose counter
-- File name: gpt.vhd
-- VHDL unit: GenPurpTimer
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED."-";
entity GenPurpTimer is
port (
MECHalt_Int_N : IN Std_Logic;
D_Int_In : IN Std_Logic_Vector(31 downto 0);
DPar_Int_In : IN Std_Logic;
Clk_Int : IN Std_Logic;
Reset_Int_N : IN Std_Logic;
Wr_Int_N : IN Std_Logic;
CounterLoad : IN Std_Logic;
ReLoad : IN Std_Logic;
ScalerLoad : IN Std_Logic;
ScalerHold : IN Std_Logic;
GPT_CountReg_N : IN Std_Logic;
GPT_ScalerReg_N : IN Std_Logic;
ParErrGPTim : OUT Std_Logic;
CPar_GPTim : OUT Std_Logic;
SPar_GPTim : OUT Std_Logic;
GPTimTO : OUT Std_Logic;
S_GPTim : OUT Std_Logic_Vector(16 downto 1);
C_GPTim : OUT Std_Logic_Vector(31 downto 0) );
end GenPurpTimer ;
architecture Mini_Spec of GenPurpTimer is
constant ScalerWidth : integer := 16;
signal ScalerReg : Std_Logic_Vector(ScalerWidth downto 0);
signal ScalerCountDff : Std_Logic_Vector(ScalerWidth downto 0);
signal ScalerCount : Std_Logic_Vector(ScalerWidth downto 0);
signal ScalerCounti : Std_Logic_Vector(ScalerWidth downto 0);
signal CounterReg : Std_Logic_Vector(32 downto 0);
signal CounterCount : Std_Logic_Vector(32 downto 0);
signal CounterCounti : Std_Logic_Vector(32 downto 0);
signal CounterCountDff : Std_Logic_Vector(32 downto 0);
signal DPar_Scaler : Std_Logic;
signal DPar_Count : Std_Logic;
signal TimeOut_Generatedi : Std_Logic;
signal TimeOut_Generated_rck : Std_Logic;
begin
----------------------------------------------------------------------------
Registers: process(Reset_Int_N,Clk_int)
begin
if Reset_Int_N = '0' then --Reset Registers
ScalerReg <= (others => '1');
CounterReg <= (others => '1');
elsif Clk_Int'event and Clk_Int='0' then
if Wr_Int_N = '0' then -- Write edge
--Write Scaler Register
if GPT_ScalerReg_N = '0' then
ScalerReg <= DPar_Int_In & D_Int_In(ScalerWidth-1 downto 0);
end if;
--Write Counter Register
if GPT_CountReg_N = '0' then
CounterReg <= DPar_Int_In & D_Int_In;
end if;
end if;
end if;
end process;
-- Check Parity
ParErrGPTim <=
ParityCheck(ScalerCountDff(ScalerWidth-1 downto 0),
ScalerCountDff(ScalerWidth)) or
ParityCheck(CounterCountDff(31 downto 0),CounterCountDff(32));
-- Read Timer
C_GPTim <= CounterCountDff(31 downto 0);
CPar_GPTim <= CounterCountDff(32);
S_GPTim <= ScalerCountDff(ScalerWidth-1 downto 0);
SPar_GPTim <= ScalerCountDff(ScalerWidth) ;
----------------------------------------------------------------------------
Scaler: process(Reset_Int_N,Clk_Int)
begin
if Reset_Int_N = '0' then
ScalerCountDff <= (others => '1');
CounterCountDff <= (others => '1');
TimeOut_Generated_rck <= '0';
elsif Clk_Int'event and Clk_Int='1' then
if not (MECHalt_Int_N = '0') then
CounterCountDff <= CounterCounti;
ScalerCountDff <= ScalerCounti;
end if;
TimeOut_Generated_rck <= TimeOut_Generatedi;
end if;
end process;
ScalerCounti <= ScalerCountDff when ScalerHold = '1' else
ScalerReg(ScalerWidth) &
ScalerReg(ScalerWidth-1 downto 0) when
((CounterLoad or ScalerLoad or ScalerCount(ScalerWidth)) = '1') else
(DPar_Scaler & ScalerCount(ScalerWidth-1 downto 0));
CounterCounti <= CounterCountDff when ScalerHold = '1' else
CounterReg when ((CounterLoad or
(CounterCount(32) and ReLoad)) = '1') else
(DPar_Count & CounterCount(31 downto 0)) when
(ScalerCount(ScalerWidth) and not CounterCount(32)) = '1' else
CounterCountDff;
TimeOut_Generatedi <=
'1' when (CounterCount(32) = '1') else
'0';
GPTimTO <= TimeOut_Generatedi and not TimeOut_Generated_rck;
ScalerCount <= ('0' & ScalerCountDff(ScalerWidth-1 downto 0)) - 1 when
not is_x(ScalerCountDff(ScalerWidth-1 downto 0)) else
"XXXXXXXXXXXXXXXXX";
DPar_Scaler <= ParityGen(ScalerCount(ScalerWidth-1 downto 0) );
CounterCount <= ('0' & CounterCountDff(31 downto 0)) - 1 when
not is_x(CounterCountDff(31 downto 0)) else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
DPar_Count <= ParityGen(CounterCount(31 downto 0));
end Mini_Spec ;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: RTC counter
-- File name: rtc.vhd
-- VHDL unit: RTCTimer
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED."-";
entity RTCTimer is
port (
MECHalt_Int_N : IN Std_Logic;
D_Int_In : IN Std_Logic_Vector(31 downto 0);
DPar_Int_In : IN Std_Logic;
Clk_Int : IN Std_Logic;
Reset_Int_N : IN Std_Logic;
Wr_Int_N : IN Std_Logic;
CounterLoad_RTC : IN Std_Logic;
ReLoad_RTC : IN Std_Logic;
ScalerLoad_RTC : IN Std_Logic;
ScalerHold_RTC : IN Std_Logic;
RTC_CountReg_N : IN Std_Logic;
RTC_ScalerReg_N : IN Std_Logic;
ParErr_RTCTim : OUT Std_Logic;
SPar_RTCTim : OUT Std_Logic;
CPar_RTCTim : OUT Std_Logic;
RTCTimTO : OUT Std_Logic;
S_RTCTim : OUT Std_Logic_Vector(8 downto 1);
C_RTCTim : OUT Std_Logic_Vector(31 downto 0)
);
end RTCTimer;
architecture Mini_Spec of RTCTimer is
constant ScalerWidth : integer := 8;
signal TimeOut_Generated : Std_Logic ;
signal ScalerReg : Std_Logic_Vector(ScalerWidth downto 0);
signal ScalerCountDff : Std_Logic_Vector(ScalerWidth downto 0);
signal ScalerCount : Std_Logic_Vector(ScalerWidth downto 0);
signal ScalerCounti : Std_Logic_Vector(ScalerWidth downto 0);
signal CounterReg : Std_Logic_Vector(32 downto 0);
signal CounterCount : Std_Logic_Vector(32 downto 0);
signal CounterCounti : Std_Logic_Vector(32 downto 0);
signal CounterCountDff : Std_Logic_Vector(32 downto 0);
signal DPar_Scaler : Std_Logic;
signal DPar_Count : Std_Logic;
signal TimeOut_Generatedi : Std_Logic;
signal TimeOut_Generated_rck : Std_Logic;
begin
----------------------------------------------------------------------------
Registers: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N = '0' then
ScalerReg <= (others => '1');
CounterReg <= (others => '1');
elsif Clk_Int'event and Clk_Int='0' then
if Wr_Int_N = '0' then -- Write edge
if RTC_ScalerReg_N = '0' then
ScalerReg <= DPar_Int_In & D_Int_In(ScalerWidth-1 downto 0);
end if;
if RTC_CountReg_N = '0' then
CounterReg <= DPar_Int_In & D_Int_In;
end if;
end if;
end if;
end process;
-- Check Parity
ParErr_RTCTim <=
ParityCheck(ScalerCountDff(ScalerWidth-1 downto 0),
ScalerCountDff(ScalerWidth)) or
ParityCheck(CounterCountDff(31 downto 0),CounterCountDff(32));
-- Read Timer
C_RTCTim <= CounterCountDff(31 downto 0);
CPar_RTCTim <= CounterCountDff(32);
S_RTCTim <= ScalerCountDff(ScalerWidth-1 downto 0);
SPar_RTCTim <= ScalerCountDff(ScalerWidth);
----------------------------------------------------------------------------
Scaler: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N = '0' then
ScalerCountDff <= (others => '1');
CounterCountDff <= (others => '1');
TimeOut_Generated_rck <= '0';
elsif Clk_Int'event and Clk_Int ='1' then
if not (MECHalt_Int_N = '0') then
CounterCountDff <= CounterCounti;
ScalerCountDff <= ScalerCounti;
end if;
TimeOut_Generated_rck <= TimeOut_Generatedi;
end if;
end process;
ScalerCounti <= ScalerCountDff when ScalerHold_RTC = '1' else
ScalerReg(ScalerWidth) &
ScalerReg(ScalerWidth-1 downto 0) when
((CounterLoad_RTC or ScalerLoad_RTC or ScalerCount(ScalerWidth)) = '1') else
(DPar_Scaler & ScalerCount(ScalerWidth-1 downto 0));
CounterCounti <= CounterCountDff when ScalerHold_RTC = '1' else
CounterReg when ((CounterLoad_RTC or
(CounterCount(32) and ReLoad_RTC)) = '1') else
(DPar_Count & CounterCount(31 downto 0)) when
(ScalerCount(ScalerWidth) and not (CounterCount(32))) = '1' else
CounterCountDff;
TimeOut_Generatedi <=
'1' when (CounterCount(32) = '1') else
'0';
RTCTimTO <= TimeOut_Generatedi and not TimeOut_Generated_rck;
ScalerCount <= ('0' & ScalerCountDff(ScalerWidth-1 downto 0)) - 1 when
not is_x(ScalerCountDff(ScalerWidth-1 downto 0)) else
"XXXXXXXXX";
DPar_Scaler <= ParityGen(ScalerCount(ScalerWidth-1 downto 0));
CounterCount <= ('0' & CounterCountDff(31 downto 0)) - 1 when
not is_x(CounterCountDff(31 downto 0)) else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
DPar_Count <= ParityGen(CounterCount(31 downto 0));
end Mini_Spec ;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: Timer control
-- File name: timmux.vhd
-- VHDL unit: TimerControl
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity TimerControl is
port (
SPar_GPTim_A : in Std_Logic;
CPar_GPTim_A : in Std_Logic;
SPar_RTCTim : in Std_Logic;
CPar_RTCTim : in Std_Logic;
S_RTCTim : in Std_Logic_Vector(8 downto 1);
C_RTCTim : in Std_Logic_Vector(31 downto 0);
S_GPTim_A : in Std_Logic_Vector(16 downto 1);
C_GPTim_A : in Std_Logic_Vector(31 downto 0);
ParErr_RTCTim : in Std_Logic;
ParErrGPTim_A : in Std_Logic;
ParityError_Tim : out Std_Logic;
D_Tim_Out : out Std_Logic_Vector(31 downto 0);
DPar_Tim_Out : out Std_Logic;
D_Int_In : in Std_Logic_Vector(31 downto 0);
Clk_Int : in Std_Logic;
Reset_Int_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
GPT_A_CountReg_N : in Std_Logic;
GPT_A_ScalerReg_N : in Std_Logic;
RTC_CountReg_N : in Std_Logic;
RTC_ScalerReg_N : in Std_Logic;
TimerControlReg_N : in Std_Logic;
CounterLoad_A : out Std_Logic;
ReLoad_A : out Std_Logic;
ScalerLoad_A : out Std_Logic;
ScalerHold_A : out Std_Logic;
CounterLoad_RTC : out Std_Logic;
ReLoad_RTC : out Std_Logic;
ScalerLoad_RTC : out Std_Logic;
ScalerHold_RTC : out Std_Logic);
end TimerControl;
architecture Mini_Spec of TimerControl is
signal TimerCtrl_Reg : Std_Logic_Vector(11 downto 0);
signal TimerCtrl_Par : Std_Logic;
signal TimerCtrlParCheck : Std_Logic;
begin
----------------------------------------------------------------------------
Mux: process(CPar_RTCTim, C_RTCTim, RTC_CountReg_N,
SPar_RTCTim, S_RTCTim, RTC_ScalerReg_N,
CPar_GPTim_A, C_GPTim_A, GPT_A_CountReg_N,
SPar_GPTim_A, S_GPTim_A, GPT_A_ScalerReg_N)
begin
for i in 0 to 7 loop
D_Tim_Out(i) <= (C_RTCTim(i) and not (RTC_CountReg_N)) or
(S_RTCTim(i+1) and not (RTC_ScalerReg_N)) or
(C_GPTim_A(i) and not (GPT_A_CountReg_N)) or
(S_GPTim_A(i+1) and not (GPT_A_ScalerReg_N));
end loop;
for i in 8 to 15 loop
D_Tim_Out(i) <= (C_RTCTim(i) and not (RTC_CountReg_N)) or
(C_GPTim_A(i) and not (GPT_A_CountReg_N)) or
(S_GPTim_A(i+1) and not (GPT_A_ScalerReg_N));
end loop;
for i in 16 to 31 loop
D_Tim_Out(i) <= (C_RTCTim(i) and not (RTC_CountReg_N)) or
(C_GPTim_A(i) and not (GPT_A_CountReg_N));
end loop;
DPar_Tim_Out <= (CPar_RTCTim and not (RTC_CountReg_N)) or
(SPar_RTCTim and not (RTC_ScalerReg_N)) or
(CPar_GPTim_A and not (GPT_A_CountReg_N)) or
(SPar_GPTim_A and not (GPT_A_ScalerReg_N));
end process;
TimerCtrl_Reg(7 downto 4) <= "0000";
TimControlReg : process(Reset_Int_N, Clk_Int)
begin
-- wait until Clk_Int'event and Clk_Int='0';
if Reset_Int_N = '0' then
TimerCtrl_Reg(3 downto 0) <= "0000";
TimerCtrl_Reg(11 downto 8) <= "0001";
TimerCtrl_Par <= '0';
elsif Clk_Int'event and Clk_Int='0' then
if Wr_Int_N = '0' and TimerControlReg_N = '0' then
TimerCtrl_Reg(3 downto 0) <= D_Int_In(3 downto 0);
TimerCtrl_Reg(11 downto 8) <= D_Int_In(11 downto 8);
TimerCtrl_Par <= not (D_Int_In(0) xor D_Int_In(2) xor
D_Int_In(8) xor D_Int_In(10));
else
TimerCtrl_Reg(1) <= '0';
TimerCtrl_Reg(3) <= '0';
TimerCtrl_Reg(9) <= '0';
TimerCtrl_Reg(11) <= '0';
end if;
end if;
end process;
ReLoad_A <= TimerCtrl_Reg(0);
CounterLoad_A <= TimerCtrl_Reg(1);
ScalerHold_A <= not TimerCtrl_Reg(2);
ScalerLoad_A <= TimerCtrl_Reg(3);
ReLoad_RTC <= TimerCtrl_Reg(8);
CounterLoad_RTC <= TimerCtrl_Reg(9);
ScalerHold_RTC <= not TimerCtrl_Reg(10);
ScalerLoad_RTC <= TimerCtrl_Reg(11);
TimerCtrlParCheck <= TimerCtrl_Par xor
not (TimerCtrl_Reg(0) xor TimerCtrl_Reg(2) xor
TimerCtrl_Reg(8) xor TimerCtrl_Reg(10));
ParityError_Tim <= TimerCtrlParCheck or ParErr_RTCTim or ParErrGPTim_A;
end Mini_Spec ;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: Timer
-- File name: \mec\source\timers.vhd
-- VHDL unit: Timers
-- Purpose and functionality: (Text)
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
entity Timers is
port (
Clk_Int : in Std_Logic;
Reset_Int_N : in Std_Logic;
MECHalt_Int_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
GPT_A_CountReg_N : in Std_Logic;
GPT_A_ScalerReg_N : in Std_Logic;
RTC_CountReg_N : in Std_Logic;
RTC_ScalerReg_N : in Std_Logic;
TimerControlReg_N : in Std_Logic;
D_Int_In : in Std_Logic_Vector(31 downto 0);
DPar_Int_In : in Std_Logic;
ParityError_Tim : out Std_Logic;
D_Tim_Out : out Std_Logic_Vector(31 downto 0);
DPar_Tim_Out : out Std_Logic;
GPTimTO_A : out Std_Logic;
RTCTimTO : out Std_Logic
);
end Timers;
architecture Mini_Spec of Timers is
component TimerControl
port (
SPar_GPTim_A : in Std_Logic;
CPar_GPTim_A : in Std_Logic;
SPar_RTCTim : in Std_Logic;
CPar_RTCTim : in Std_Logic;
S_RTCTim : in Std_Logic_Vector(8 downto 1);
C_RTCTim : in Std_Logic_Vector(31 downto 0);
S_GPTim_A : in Std_Logic_Vector(16 downto 1);
C_GPTim_A : in Std_Logic_Vector(31 downto 0);
ParErr_RTCTim : in Std_Logic;
ParErrGPTim_A : in Std_Logic;
ParityError_Tim : OUT Std_Logic;
D_Tim_Out : OUT Std_Logic_Vector(31 downto 0);
DPar_Tim_Out : OUT Std_Logic;
D_Int_In : in Std_Logic_Vector(31 downto 0);
Clk_Int : in Std_Logic;
Reset_Int_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
GPT_A_CountReg_N : in Std_Logic;
GPT_A_ScalerReg_N : in Std_Logic;
RTC_CountReg_N : in Std_Logic;
RTC_ScalerReg_N : in Std_Logic;
TimerControlReg_N : in Std_Logic;
CounterLoad_A : OUT Std_Logic;
ReLoad_A : OUT Std_Logic;
ScalerLoad_A : OUT Std_Logic;
ScalerHold_A : OUT Std_Logic;
CounterLoad_RTC : OUT Std_Logic;
ReLoad_RTC : OUT Std_Logic;
ScalerLoad_RTC : OUT Std_Logic;
ScalerHold_RTC : OUT Std_Logic );
end component;
component RTCTimer
port (
--
MECHalt_Int_N : in Std_Logic;
--
D_Int_In : in Std_Logic_Vector(31 downto 0);
DPar_Int_In : in Std_Logic;
Clk_Int : in Std_Logic;
Reset_Int_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
CounterLoad_RTC : in Std_Logic;
ReLoad_RTC : in Std_Logic;
ScalerLoad_RTC : in Std_Logic;
ScalerHold_RTC : in Std_Logic;
RTC_CountReg_N : in Std_Logic;
RTC_ScalerReg_N : in Std_Logic;
ParErr_RTCTim : OUT Std_Logic;
SPar_RTCTim : OUT Std_Logic;
CPar_RTCTim : OUT Std_Logic;
RTCTimTO : OUT Std_Logic;
S_RTCTim : OUT Std_Logic_Vector(8 downto 1);
C_RTCTim : OUT Std_Logic_Vector(31 downto 0)
);
end component;
component GenPurpTimer
port (
--
MECHalt_Int_N : in Std_Logic;
--
D_Int_In : in Std_Logic_Vector(31 downto 0);
DPar_Int_In : in Std_Logic;
Clk_Int : in Std_Logic;
Reset_Int_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
CounterLoad : in Std_Logic;
ReLoad : in Std_Logic;
ScalerLoad : in Std_Logic;
ScalerHold : in Std_Logic;
GPT_CountReg_N : in Std_Logic;
GPT_ScalerReg_N : in Std_Logic;
ParErrGPTim : OUT Std_Logic;
CPar_GPTim : OUT Std_Logic;
SPar_GPTim : OUT Std_Logic;
GPTimTO : OUT Std_Logic;
S_GPTim : OUT Std_Logic_Vector(16 downto 1);
C_GPTim : OUT Std_Logic_Vector(31 downto 0)
);
end component;
signal ParErrGPTim_A : Std_Logic;
signal SPar_GPTim_A : Std_Logic;
signal CPar_GPTim_A : Std_Logic;
signal S_GPTim_A : Std_Logic_Vector(16 downto 1);
signal C_GPTim_A : Std_Logic_Vector(31 downto 0);
-- signal ParErrGPTim_B : Std_Logic;
-- signal SPar_GPTim_B : Std_Logic;
-- signal CPar_GPTim_B : Std_Logic;
-- signal S_GPTim_B : Std_Logic_Vector(16 downto 1);
-- signal C_GPTim_B : Std_Logic_Vector(31 downto 0);
signal ParErr_RTCTim : Std_Logic;
signal SPar_RTCTim : Std_Logic;
signal CPar_RTCTim : Std_Logic;
signal S_RTCTim : Std_Logic_Vector(8 downto 1);
signal C_RTCTim : Std_Logic_Vector(31 downto 0);
signal CounterLoad_A : Std_Logic;
signal ReLoad_A : Std_Logic;
signal ScalerLoad_A : Std_Logic;
signal ScalerHold_A : Std_Logic;
signal CounterLoad_B : Std_Logic;
signal ReLoad_B : Std_Logic;
signal ScalerLoad_B : Std_Logic;
signal ScalerHold_B : Std_Logic;
signal CounterLoad_RTC : Std_Logic;
signal ReLoad_RTC : Std_Logic;
signal ScalerLoad_RTC : Std_Logic;
signal ScalerHold_RTC : Std_Logic;
begin
TimerControl_1 : TimerControl
port map (
SPar_GPTim_A => SPar_GPTim_A,
CPar_GPTim_A => CPar_GPTim_A,
-- SPar_GPTim_B => SPar_GPTim_B,
-- CPar_GPTim_B => CPar_GPTim_B,
SPar_RTCTim => SPar_RTCTim,
CPar_RTCTim => CPar_RTCTim,
S_RTCTim => S_RTCTim,
C_RTCTim => C_RTCTim,
S_GPTim_A => S_GPTim_A,
C_GPTim_A => C_GPTim_A,
-- S_GPTim_B => S_GPTim_B,
-- C_GPTim_B => C_GPTim_B,
ParErr_RTCTim => ParErr_RTCTim,
ParErrGPTim_A => ParErrGPTim_A,
-- ParErrGPTim_B => ParErrGPTim_B,
ParityError_Tim => ParityError_Tim,
D_Tim_Out => D_Tim_Out,
DPar_Tim_Out => DPar_Tim_Out,
D_Int_In => D_Int_In,
Clk_Int => Clk_Int,
Reset_Int_N => Reset_Int_N,
Wr_Int_N => Wr_Int_N,
GPT_A_CountReg_N => GPT_A_CountReg_N,
GPT_A_ScalerReg_N => GPT_A_ScalerReg_N,
RTC_CountReg_N => RTC_CountReg_N,
RTC_ScalerReg_N => RTC_ScalerReg_N,
TimerControlReg_N => TimerControlReg_N,
CounterLoad_A => CounterLoad_A,
ReLoad_A => ReLoad_A,
ScalerLoad_A => ScalerLoad_A,
ScalerHold_A => ScalerHold_A,
CounterLoad_RTC => CounterLoad_RTC,
ReLoad_RTC => ReLoad_RTC,
ScalerLoad_RTC => ScalerLoad_RTC,
ScalerHold_RTC => ScalerHold_RTC );
RTCTimer_1 : RTCTimer
port map (
MECHalt_Int_N => MECHalt_Int_N,
D_Int_In => D_Int_In,
DPar_Int_In => DPar_Int_In,
Clk_Int => Clk_Int,
Reset_Int_N => Reset_Int_N,
Wr_Int_N => Wr_Int_N,
CounterLoad_RTC => CounterLoad_RTC,
ReLoad_RTC => ReLoad_RTC,
ScalerLoad_RTC => ScalerLoad_RTC,
ScalerHold_RTC => ScalerHold_RTC,
RTC_CountReg_N => RTC_CountReg_N,
RTC_ScalerReg_N => RTC_ScalerReg_N,
ParErr_RTCTim => ParErr_RTCTim,
SPar_RTCTim => SPar_RTCTim,
CPar_RTCTim => CPar_RTCTim,
RTCTimTO => RTCTimTO,
S_RTCTim => S_RTCTim,
C_RTCTim => C_RTCTim );
GenPurpTimer_A : GenPurpTimer
port map (
MECHalt_Int_N => MECHalt_Int_N,
D_Int_In => D_Int_In,
DPar_Int_In => DPar_Int_In,
Clk_Int => Clk_Int,
Reset_Int_N => Reset_Int_N,
Wr_Int_N => Wr_Int_N,
CounterLoad => CounterLoad_A,
ReLoad => ReLoad_A,
ScalerLoad => ScalerLoad_A,
ScalerHold => ScalerHold_A,
GPT_CountReg_N => GPT_A_CountReg_N,
GPT_ScalerReg_N => GPT_A_ScalerReg_N,
ParErrGPTim => ParErrGPTim_A,
CPar_GPTim => CPar_GPTim_A,
SPar_GPTim => SPar_GPTim_A,
GPTimTO => GPTimTO_A,
S_GPTim => S_GPTim_A,
C_GPTim => C_GPTim_A );
end Mini_Spec;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title:
-- File name:
-- VHDL unit: (Type)
-- Purpose and functionality: (Text)
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
entity TAP is
port(
TRST_In_N : in Std_Logic;
TCK_In : in Std_Logic;
TDI_In : in Std_Logic;
TMS_In : in Std_Logic;
TDO_Out : out Std_Logic
);
end TAP;
architecture Mini_Spec of TAP is
type TAP_State is (Reset, Idle,
Sel_DR_Scan, Capture_DR, Shift_DR, Exit1_DR, Pause_DR, Exit2_DR, Update_DR,
Sel_IR_Scan, Capture_IR, Shift_IR, Exit1_IR, Pause_IR, Exit2_IR, Update_IR);
signal State : TAP_State;
signal TDOInternal : Std_Logic;
begin
TAPControl: process (TRST_In_N,TCK_In)
variable TMSInternal : Std_Logic;
variable TDIInternal : Std_Logic;
variable Bypass_Shift : Std_Logic;
variable IR_Reg : Std_Logic_Vector (0 to 1);
variable IR_Shift : Std_Logic_Vector (0 to 1);
variable IntScan_Reg : Std_Logic_Vector (0 to 2);
variable IntScan_Shift : Std_Logic_Vector (0 to 2);
begin
if TRST_In_N = '0' then -- Asynchronous reset
State <= Reset;
IntScan_Reg := "101";
elsif TCK_In'event and TCK_In = '1' then
TMSInternal := TMS_In;
TDIInternal := TDI_In;
case State is
when Reset =>
IR_Reg := "00"; -- Bypass instruction
IR_Shift := "00";
Bypass_Shift := '0';
if TMSInternal = '1' then
State <= Reset;
else
State <= Idle;
end if;
when Idle =>
if TMSInternal = '1' then
State <= Sel_DR_Scan;
end if;
when Sel_DR_Scan =>
if TMSInternal = '1' then
State <= Sel_IR_Scan;
else
State <= Capture_DR;
end if;
when Capture_DR =>
case IR_Reg is
when "11" => -- Capture bypass register
TDOInternal <= Bypass_Shift;
when "01" => -- Capture internal scan
IntScan_Shift := IntScan_Reg;
TDOInternal <= IntScan_Shift (0);
when "10" => -- Capture boundary scan is not implemented.
null;
when others =>
null;
end case;
if TMSInternal = '1' then
State <= Exit1_DR;
else
State <= Shift_DR;
end if;
when Shift_DR =>
case IR_Reg is
when "11" => --Bypass
Bypass_Shift := TDIInternal;
TDOInternal <= Bypass_Shift;
when "01" => --Internal Scan
IntScan_Shift(0 to 1) := IntScan_Shift(1 to 2);
IntScan_Shift(2) := TDIInternal;
TDOInternal <= IntScan_Shift(0);
when "10" => --Boundary scan is not implemented.
null;
when others =>
null;
end case;
if TMSInternal = '1' then
State <= Exit1_DR;
else
State <= Shift_DR;
end if;
when Exit1_DR =>
if TMSInternal = '1' then
State <= Update_DR;
else
State <= Pause_DR;
end if;
when Pause_DR =>
if TMSInternal = '1' then
State <= Exit2_DR;
else
State <= Pause_DR;
end if;
when Exit2_DR =>
if TMSInternal = '1' then
State <= Update_DR;
else
State <= Shift_DR;
end if;
when Update_DR =>
case IR_Reg is
when "01" => -- Update chip from internal scan register
IntScan_Reg := IntScan_Shift;
when "10" => -- Update chip from boundary scan register is
null; -- not implemented.
when others =>
null;
end case;
if TMSInternal = '1' then
State <= Sel_DR_Scan;
else
State <= Idle;
end if;
when Sel_IR_Scan =>
if TMSInternal = '1' then
State <= Reset;
else
State <= Capture_IR;
end if;
when Capture_IR =>
IR_Shift := IR_Reg;
if TMSInternal = '1' then
State <= Exit1_IR;
else
State <= Shift_IR;
end if;
TDOInternal <= IR_Shift (0);
when Shift_IR =>
IR_Shift(0) := IR_Shift(1);
IR_Shift(1) := TDIInternal;
TDOInternal <= IR_Shift (0);
if TMSInternal = '1' then
State <= Exit1_IR;
else
State <= Shift_IR;
end if;
when Exit1_IR =>
if TMSInternal = '1' then
State <= Update_IR;
else
State <= Pause_IR;
end if;
when Pause_IR =>
if TMSInternal = '1' then
State <= Exit2_IR;
else
State <= Pause_IR;
end if;
when Exit2_IR =>
if TMSInternal = '1' then
State <= Update_IR;
else
State <= Shift_IR;
end if;
when Update_IR =>
IR_Reg := IR_Shift;
if TMSInternal = '1' then
State <= Sel_DR_Scan;
else
State <= Idle;
end if;
end case;
end if;
end process;
OUTPUTS : process (TCK_In)
begin
if TCK_In'event and TCK_In ='0' then
if State = Shift_DR or State = Shift_IR then
TDO_Out <= TDOInternal;
else
TDO_Out <= '0';
end if;
end if;
end process;
end Mini_Spec;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title:
-- File name: FAULT.VHD
-- VHDL unit: Fault_Handler(Mini_Spec)
-- Purpose and functionality: To handle asynchronous and synchronous fault.
-- To manage the SFFR register.
-- To generate a load signal (Load_Fault_N) to
-- enable loading of the FFAR register.
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity Fault_Handler is
port (
Clk_Int : in Std_Logic;
Rd_Int_In : in Std_Logic;
NewCycle : in Std_Logic;
SFSRTmp_UD : in Std_Logic;
Reset_Int_N : in Std_Logic;
Reset_Out_N : in std_logic;
SysFSReg_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
Instr_Fetch : in Std_Logic;
Null_Int_rck : in Std_Logic;
SysBus_Error : in Std_Logic;
BusTimeOut : in Std_Logic;
NCError_ck1 : in Std_Logic;
Unimpl_Address_Out : in Std_Logic;
Illegal_Address_Out : in Std_Logic;
MemAccess_Violation_Out : in Std_Logic;
APar_Error : in Std_Logic;
DPar_Error_ck1 : in Std_Logic;
CtlPar_Error : in Std_Logic;
DMATimeOut : in Std_Logic;
DMAInPrgs : in Std_Logic;
Intr_UART_Err : in Std_Logic;
CError_ck1 : in Std_Logic;
CError_g_rck : out Std_Logic;
WDInterrupt : in Std_Logic;
AccessType : in Std_Logic_Vector(3 downto 0);
Load_FFAR_N : out Std_Logic;
D_Fault_Out : out std_logic_Vector(31 downto 0);
DPar_Fault_Out : out Std_Logic;
ParityErrorFault : out Std_Logic;
Intr_DMAAcc : buffer Std_Logic;
MExc_Int : out Std_Logic;
Write_Inhibit : out Std_Logic
);
end Fault_Handler;
architecture Mini_Spec of Fault_Handler is
signal SFSR_Reg : Std_Logic_Vector(15 downto 0);
signal SFSR_Par : Std_Logic;
function Syn_Fault_Nr ( Vec : Std_Logic_Vector ) return Std_Logic_Vector is
variable FaultType : Std_logic_Vector(3 downto 0);
begin
if Vec(0) = '1' then
FaultType := "0000";
elsif Vec(1) = '1' then
FaultType := "0001";
elsif Vec(2) = '1' then
FaultType := "0010";
elsif Vec(3) = '1' then
FaultType := "0011";
elsif Vec(4) = '1' then
FaultType := "0100";
elsif Vec(5) = '1' then
FaultType := "0101";
elsif Vec(6) = '1' then
FaultType := "0110";
elsif Vec(7) = '1' then
FaultType := "0111";
elsif Vec(8) = '1' then
FaultType := "1000";
elsif Vec(9) = '1' then
FaultType := "1001";
else
FaultType := "1111";
end if;
return FaultType;
end Syn_Fault_Nr;
function Trap(Vec : Std_logic_Vector) return Std_Logic is
begin
return Vec(0) or Vec(1) or Vec(2) or Vec(3) or
Vec(4) or Vec(5) or Vec(6) or Vec(7) or
Vec(8) or Vec(9);
end Trap;
signal Syn_Fault_Type : Std_Logic_Vector(3 downto 0);
signal Syn_Data_Exc_N : Std_Logic;
signal UnImplArea_Int_rck : Std_Logic;
signal MECRegAcc_Error_Int_rck : Std_Logic;
signal ProtectArea_rck : Std_Logic;
signal AddrPar_Error_rck : Std_Logic;
signal CtlPar_Error_rck : Std_Logic;
signal Instr_Fetch_Int_rck : Std_Logic;
signal BusTimeOut_foo : Std_Logic;
signal BusTimeOut_g : Std_Logic;
signal SysBus_Error_foo : Std_Logic;
signal SysBus_Error_g : Std_Logic;
signal SFSRTmp_UD_rck : Std_Logic;
signal AccessType_rck : Std_Logic_Vector(3 downto 0);
signal SFSR_Tmp : Std_Logic_Vector(15 downto 0);
signal Update_SFSR : Std_Logic;
signal SynFaultVec : Std_Logic_Vector(0 to 9);
signal Intr_DMAAcc_WEE : Std_Logic;
signal CError_rck : Std_Logic;
signal NCError_foo_rck : Std_Logic;
signal DPar_Error_foo_rck : Std_Logic;
signal NCError_g : Std_Logic;
signal DPar_Error_g : Std_Logic;
signal DPar_Error_g_rck : Std_Logic;
signal DPar_Error_g_fck : Std_Logic;
signal CError_ck0 : Std_Logic;
signal NCError_ck0 : Std_Logic;
signal DPar_Error_ck0 : Std_Logic;
signal NCError_g0 : Std_Logic;
signal DPar_Error_g0 : Std_Logic;
signal DMATimeOut_rck : Std_Logic;
signal DMATimeOut_rck1 : Std_Logic;
signal DMATimeOut_rckedge : Std_Logic;
signal Intr_DMAAcc_Int : Std_Logic;
signal Intr_DMAAcc_rck : Std_Logic;
signal Intr_DMAAcc_rck1 : Std_Logic;
signal MExc_Int_loc : Std_Logic;
signal Write_Inhibit_loc : Std_Logic;
signal NonDataError_rck : Std_Logic;
signal ResetRckSample_N : Std_Logic;
begin
SynFaultVec <= CtlPar_Error_rck & DPar_Error_g & AddrPar_Error_rck &
ProtectArea_rck & UnImplArea_Int_rck & '0' &
MECRegAcc_Error_Int_rck & NCError_g & BusTimeOut_g &
SysBus_Error_g;
Syn_Fault_Type <= Syn_Fault_Nr(SynFaultVec);
-- Sampled on CK+
MExc_Int_loc_Gen: process(SysBus_Error_g, BusTimeOut_g, Unimpl_Address_Out,
Illegal_Address_Out, APar_Error, CtlPar_Error, DPar_Error_g)
begin
MExc_Int_loc <= SysBus_Error_g or
BusTimeOut_g or
Unimpl_Address_Out or
Illegal_Address_Out or
APar_Error or
CtlPar_Error or DPar_Error_g;
end process;
-- DPar_Error_g to handle properly the data parity error detected during a store
-- Data parity detected during a load is handle in the same way than NCerror.
MExc_Int <= MemAccess_Violation_Out or MExc_Int_loc or DPar_Error_ck1;
-- Sampled on CK+
Intr_DMAAccGen: process(DMAInPrgs, SysBus_Error_g, BusTimeOut_g, MECRegAcc_Error_Int_rck,
UnImplArea_Int_rck,
AddrPar_Error_rck, CtlPar_Error_rck, ProtectArea_rck)
begin
-- Load and Store Cycle last 2 cycles at least, so there is not problems to
-- rise the interrupt one clock later
Intr_DMAAcc_WEE <= DMAInPrgs and (SysBus_Error_g or BusTimeOut_g or
MECRegAcc_Error_Int_rck or UnImplArea_Int_rck or
AddrPar_Error_rck or CtlPar_Error_rck or ProtectArea_rck);
end process;
Intr_DMAAcc_Int <= Intr_DMAAcc_WEE or (DMAInPrgs and (NCError_g or DPar_Error_g));
-- Sampled on falling edge of CK2 following CK-
Write_Inhibit_loc_Gen: process(Unimpl_Address_Out, Illegal_Address_Out,
APar_Error, CtlPar_Error)
begin
Write_Inhibit_loc <= Illegal_Address_Out or
Unimpl_Address_Out or APar_Error or
CtlPar_Error;
end process;
Write_Inhibit <= MemAccess_Violation_Out or Write_Inhibit_loc or
NCError_g0 or DPar_Error_g0;
Syn_Data_Exc_N <= not(not(Instr_Fetch_Int_rck) and Trap(SynFaultVec)) or
Null_Int_rck;
-------------------------------------------------------------
-- Process that handles address exceptions and latch them ---
-------------------------------------------------------------
ResetRckSample_N <= not Null_Int_rck and Reset_Int_N;
rck_sampling1: process(ResetRckSample_N, Clk_Int)
begin
if ResetRckSample_N = '0' then
UnImplArea_Int_rck <= '0';
MECRegAcc_Error_Int_rck <= '0';
AddrPar_Error_rck <= '0';
CtlPar_Error_rck <= '0';
ProtectArea_rck <= '0';
NonDataError_rck <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
UnImplArea_Int_rck <= Illegal_Address_Out;
MECRegAcc_Error_Int_rck <= Unimpl_Address_Out;
AddrPar_Error_rck <= APar_Error;
CtlPar_Error_rck <= CtlPar_Error;
ProtectArea_rck <= MemAccess_Violation_Out;
NonDataError_rck <= CtlPar_Error_rck or AddrPar_Error_rck or
ProtectArea_rck or UnImplArea_Int_rck or
MECRegAcc_Error_Int_rck or
BusTimeOut_g or SysBus_Error_g;
end if;
end process;
rck_sampling2: process
begin
wait until Clk_Int'event and Clk_Int = '1';
Instr_Fetch_Int_rck <= Instr_Fetch;
AccessType_rck <= AccessType;
SFSRTmp_UD_rck <= SFSRTmp_UD;
DMATimeOut_rck <= DMATimeOut;
Intr_DMAAcc_rck <= Intr_DMAAcc_Int;
DMATimeOut_rck1 <= DMATimeOut_rck;
Intr_DMAAcc_rck1 <= Intr_DMAAcc_rck;
end process;
DMATimeOut_rckedge <= DMATimeOut_rck and not DMATimeOut_rck1;
Intr_DMAAcc <= Intr_DMAAcc_rck and not Intr_DMAAcc_rck1;
-------------------------------------------------------------------------------
-- SFSR Content calculation
-------------------------------------------------------------------------------
SFSR_Tmp(0) <= '0';
SFSR_Tmp(1) <= '0';
SFSR_Tmp(7) <= '0';
SFSR_Tmp(11) <= '0';
SFSRGen: process
begin
-- Handle all error inputs
wait until Clk_Int'event and Clk_Int = '1';
-- Synchronous Data exception
if (DMAInPrgs = '0' and Syn_Data_Exc_N = '0' and SFSRTmp_UD = '1') or
-- Asynchronous Fault
(SFSR_Reg(2) = '0' and
(DMATimeOut_rckedge = '1' or Intr_DMAAcc_Int = '1' or
Intr_UART_Err = '1' or WDInterrupt = '1' or
CError_ck1 = '1')) then
Update_SFSR <= '1';
else
Update_SFSR <= '0';
end if;
-- Synchronous Data exception
if (DMAInPrgs = '0' and Syn_Data_Exc_N = '0' and SFSRTmp_UD = '1') or
-- Asynchronous Fault
(SFSR_Reg(2) = '0' and
(DMATimeOut_rckedge = '1' or Intr_DMAAcc_Int = '1' or
Intr_UART_Err = '1' or WDInterrupt = '1' or
CError_ck1 = '1')) then
SFSR_Tmp(6 downto 3) <= Syn_Fault_Type;
SFSR_Tmp(15 downto 12) <= AccessType_rck;
end if;
-- Synchronous Data exception
if DMAInPrgs = '0' and Syn_Data_Exc_N = '0' and SFSRTmp_UD = '1'then
SFSR_Tmp(2) <= '1'; -- Set Synchronous Data Fault Valid
SFSR_Tmp(8) <= '0'; -- Clear Asynchronous Fault Valid
SFSR_Tmp(10 downto 9) <= SFSR_Reg(10 downto 9);
-- Asynchronous Fault
elsif SFSR_Reg(2) = '0' and
(DMATimeOut_rckedge = '1' or Intr_DMAAcc_Int = '1' or
Intr_UART_Err = '1' or WDInterrupt = '1' or
CError_ck1 = '1') then
SFSR_Tmp(2) <= SFSR_Reg(2);
SFSR_Tmp(8) <= '1';
if WDInterrupt = '1' then
SFSR_Tmp(10 downto 9) <= "00";
elsif DMATimeOut_rckedge = '1' or Intr_DMAAcc_Int = '1' then
SFSR_Tmp(10 downto 9) <= "01";
elsif Intr_UART_Err = '1' then
SFSR_Tmp(10 downto 9) <= "10";
else
SFSR_Tmp(10 downto 9) <= "11";
end if;
end if;
end process;
SFSR_Reg(0) <= '0';
SFSR_Reg(1) <= '0';
SFSRRegs: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N = '0' then
SFSR_Reg( 2) <= '0';
SFSR_Reg( 6 downto 3) <= "1111";
SFSR_Reg(15 downto 7) <= "000000000";
SFSR_Par <= '1';
elsif Clk_Int'event and Clk_Int = '0' then
if Wr_Int_N = '0' and SysFSReg_N = '0' then
-- Write only on failing edge
-- Clear the register on write
SFSR_Reg( 2) <= '0';
SFSR_Reg( 6 downto 3) <= "1111";
SFSR_Reg(15 downto 7) <= "000000000";
SFSR_Par <= '1';
elsif Update_SFSR = '1' then
SFSR_Reg(15 downto 2) <= SFSR_Tmp(15 downto 2);
SFSR_Par <= ParityGen(SFSR_Tmp(15 downto 2));
end if;
end if;
end process;
---------------------------------------------------------------------------------
-- Load FFAR and FFDR Generation
---------------------------------------------------------------------------------
-- LoadGen: process(NonDataError_rck, DPar_Error_g, NCError_g, SFSR_Reg, CError_rck,
-- Rd_Int_In, DPar_Error_g_rck)
LoadGen: process(NonDataError_rck, DPar_Error_foo_rck, NCError_foo_rck, SFSR_Reg,
CError_rck, Rd_Int_In, DPar_Error_g_rck)
begin
-- This modification has not been synthesized. A modification by hand has been
-- performed in the netlist
-- if (NonDataError_rck = '1' or DPar_Error_g = '1' or NCError_g = '1') or
if (NonDataError_rck = '1' or DPar_Error_foo_rck = '1' or NCError_foo_rck = '1') or
(Rd_Int_In = '0' and DPar_Error_g_rck = '1') then
Load_FFAR_N <= '0';
elsif SFSR_Reg(2) = '0' and SFSR_Reg(1) = '0' and SFSR_Reg(8) = '0' and
CError_rck = '1' then
Load_FFAR_N <= '0';
else
Load_FFAR_N <= '1';
end if;
end process;
------
D_Fault_Out(15 downto 0) <= SFSR_Reg;
D_Fault_Out(31 downto 16) <= "0000000000000000";
DPar_Fault_Out <= SFSR_Par;
------
ParityErrorFault <= ParityGen(SFSR_Reg) xor SFSR_Par;
---
Rcksampling: process(Reset_Out_N, Clk_Int)
begin
if Reset_Out_N = '0' then
CError_rck <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
CError_rck <= CError_ck0;
end if;
end process;
BTOsampling: process(Reset_Out_N, Clk_Int)
begin
if Reset_Out_N = '0' then
BusTimeOut_foo <= '0';
SysBus_Error_foo <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
if SFSRTmp_UD = '1' or Null_Int_rck = '1' then
BusTimeOut_foo <= '0';
SysBus_Error_foo <= '0';
else
BusTimeOut_foo <= BusTimeOut or BusTimeOut_foo;
SysBus_Error_foo <= SysBus_Error or SysBus_Error_foo;
end if;
end if;
end process;
BusTimeOut_g <= BusTimeOut_foo or BusTimeOut;
SysBus_Error_g <= SysBus_Error_foo or SysBus_Error;
ErrorSampling: process(Reset_Out_N, Clk_Int)
begin
if Reset_Out_N = '0' then
NCError_foo_rck <= '0';
DPar_Error_foo_rck <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
if DMAInPrgs = '0' and SFSRTmp_UD = '1' then
NCError_foo_rck <= '0';
DPar_Error_foo_rck <= '0';
elsif DMAInPrgs = '1' and SFSRTmp_UD_rck = '1' then
NCError_foo_rck <= '0';
DPar_Error_foo_rck <= '0';
else
NCError_foo_rck <= NCError_ck1 or NCError_foo_rck;
DPar_Error_foo_rck <= DPar_Error_ck1 or DPar_Error_foo_rck;
end if;
end if;
end process;
ErrorLatching: process(Clk_Int, CError_ck1, NCError_ck1, DPar_Error_ck1)
begin
if Clk_Int = '0' then
CError_ck0 <= CError_ck1;
NCError_ck0 <= NCError_ck1;
DPar_Error_ck0 <= DPar_Error_ck1;
end if;
end process;
NCError_g0 <= NCError_ck0 or NCError_foo_rck;
DPar_Error_g0 <= DPar_Error_ck0 or DPar_Error_foo_rck;
NCError_g <= NCError_ck1 or NCError_foo_rck;
DPar_Error_g <= DPar_Error_ck1 or DPar_Error_foo_rck;
CError_g_rck <= CError_ck1;
-- This modification has not been synthesized. A modification by hand has been
-- performed in the netlist
--Fck_smp: process(Reset_Out_N, Clk_Int)
--begin
-- if Reset_Out_N = '0' then
-- DPar_Error_g_fck <= '0';
-- elsif Clk_Int'event and Clk_Int = '0' then
-- DPar_Error_g_fck <= DPar_Error_g;
-- end if;
--end process;
Rck_smp: process(Reset_Out_N, Clk_Int)
begin
if Reset_Out_N = '0' then
DPar_Error_g_rck <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
-- DPar_Error_g_rck <= DPar_Error_g_fck;
DPar_Error_g_rck <= DPar_Error_g;
end if;
end process;
end Mini_Spec ;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: error handler
-- File name: errhandl.vhd
-- VHDL unit: Error_Handler
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity Error_Handler is
port (
Clk_Int : IN std_logic;
D_Int_In : IN std_logic_Vector(31 downto 0);
DPar_Int_In : IN std_logic;
CPUHalt_OUT_N : IN std_logic;
Reset_OUT_N : IN std_logic;
Reset_Cause : IN Std_Logic_Vector(1 downto 0);
ResetOutDetect : IN std_logic;
NoClkDetect : IN std_logic;
ErrResStatReg_N : IN std_logic;
Wr_Int_N : IN std_logic;
ErrorCtrl : IN Std_Logic_Vector(9 downto 0);
IUErr_IN_N : IN std_logic;
IUHWErr_IN_N : IN std_logic;
IUCmpErr_IN_N : IN std_logic;
FPUHWErr_IN_N : IN std_logic;
FPUCmpErr_IN_N : IN std_logic;
MecHWErr_Int_N : IN std_logic;
SWHalt_En : IN std_logic;
SysErr_OUT_N : OUT std_logic;
MecHWErr_OUT_N : OUT std_logic;
ErrorReset_N : OUT std_logic;
ErrorHalt_N : OUT std_logic;
D_Error_Out : OUT std_logic_Vector(31 downto 0);
DPar_Error_Out : OUT std_logic;
SysAv_OUT : OUT std_logic;
Int_MaskErr : OUT std_logic;
ParityErrorErrHandl : OUT std_logic
);
end Error_Handler;
architecture Mini_Spec of Error_Handler is
signal SysAv_OUT_loc : Std_Logic;
signal ERSR_Tmp : Std_Logic_Vector(5 downto 0);
signal ERSR_Shadow : Std_Logic_Vector(5 downto 0);
signal ERSR_Reg : Std_Logic_Vector(15 downto 0);
signal ERSR_Par12_0 : Std_Logic;
signal ERSR_Par15_13 : Std_Logic;
signal Errors_Sig : Std_Logic_Vector(5 downto 0);
signal Errors_ERSR : Std_Logic_Vector(5 downto 0);
signal Errors : Std_Logic_Vector(5 downto 0);
signal MaskedErrors_ERSR : Std_Logic_Vector(5 downto 0);
signal MaskedErrors : Std_Logic_Vector(5 downto 0);
signal EMR_Reg : Std_Logic_Vector(5 downto 0);
signal ResetOrHalt_N : Std_Logic_Vector(5 downto 0);
signal Int_MaskErr_rck1 : Std_Logic;
signal Int_MaskErr_rck2 : Std_Logic;
signal Int_MaskErr_fck : Std_Logic;
begin
EMR_Reg(0) <= ErrorCtrl(0);
EMR_Reg(1) <= ErrorCtrl(2);
EMR_Reg(2) <= ErrorCtrl(4);
EMR_Reg(3) <= '1';
EMR_Reg(4) <= ErrorCtrl(6);
EMR_Reg(5) <= ErrorCtrl(8);
ResetOrHalt_N(0) <= ErrorCtrl(1);
ResetOrHalt_N(1) <= ErrorCtrl(3);
ResetOrHalt_N(2) <= ErrorCtrl(5);
ResetOrHalt_N(3) <= '0';
ResetOrHalt_N(4) <= ErrorCtrl(7);
ResetOrHalt_N(5) <= ErrorCtrl(9);
----------------------------------------------------------
-- Process that controls the registers ---------
----------------------------------------------------------
ERSR_Reg(11 downto 6) <= "000000";
Regs: process
begin
wait until Clk_Int'event and Clk_Int = '0';
if ResetOutDetect = '1' then -- Reset
ERSR_Shadow <= "000000";
ERSR_Reg(5 downto 0) <= "000000";
ERSR_Reg(12) <= '0';
ERSR_Par12_0 <= '1';
if Reset_Cause = "00" then -- System Reset
ERSR_Reg(13) <= '0';
ERSR_Reg(15 downto 14) <= "00";
ERSR_Par15_13 <= '1';
else
ERSR_Reg(13) <= '0';
ERSR_Reg(15 downto 14) <= Reset_Cause;
ERSR_Par15_13 <= (Reset_Cause(1) xor ERSR_Reg(15)) xor
(Reset_Cause(0) xor ERSR_Reg(14)) xor ERSR_Par15_13;
end if;
else
if Wr_Int_N = '1' then
ERSR_Shadow <= ERSR_Shadow or ERSR_Tmp;
ERSR_Reg(5 downto 0) <= ERSR_Reg(5 downto 0) or ERSR_Tmp;
ERSR_Par12_0 <= ParityGen((ERSR_Reg(5 downto 0) or ERSR_Tmp) & ERSR_Reg(12));
elsif Wr_Int_N = '0' then
if ErrResStatReg_N = '0' then -- Write to ERSR
if SWHalt_En = '1' then
ERSR_Shadow <= D_Int_In(5 downto 0) or ERSR_Tmp;
ERSR_Reg(5 downto 0) <= D_Int_In(5 downto 0) or ERSR_Tmp;
ERSR_Reg(12) <= D_Int_In(12);
ERSR_Par12_0 <= ParityGen((D_Int_In(12) & "00000" & D_Int_In(5 downto 0)) or
("000000" & ERSR_Tmp));
else -- always allow writing to system availabilty flag
ERSR_Reg(12) <= D_Int_In(12);
ERSR_Par12_0 <= ERSR_Par12_0 xor (ERSR_Reg(12) xor D_Int_In(12));
end if;
end if;
end if;
if (CPUHalt_OUT_N = '0') then -- IU/FPU Halted
ERSR_Reg(13) <= '1';
ERSR_Par15_13 <= ERSR_Par15_13 xor (not(ERSR_Reg(13)));
end if;
end if;
end process;
-----
SamplPin: process(Reset_OUT_N, Clk_Int)
begin
if Reset_OUT_N = '0' then
ERSR_Tmp <= "000000";
elsif Clk_Int'event and Clk_Int = '1' then
if IUErr_IN_N = '0' then
ERSR_Tmp(0) <= '1';
else
ERSR_Tmp(0) <= '0';
end if;
if IUHWErr_IN_N = '0' then
ERSR_Tmp(1) <= '1';
else
ERSR_Tmp(1) <= '0';
end if;
if IUCmpErr_IN_N = '0' and (ERSR_Reg(1) = '0') then
ERSR_Tmp(2) <= '1';
else
ERSR_Tmp(2) <= '0';
end if;
if FPUHWErr_IN_N = '0' then
ERSR_Tmp(3) <= '1';
else
ERSR_Tmp(3) <= '0';
end if;
if FPUCmpErr_IN_N = '0' and (ERSR_Reg(3) = '0') then
ERSR_Tmp(4) <= '1';
else
ERSR_Tmp(4) <= '0';
end if;
if MecHWErr_Int_N = '0' then
ERSR_Tmp(5) <= '1';
else
ERSR_Tmp(5) <= '0';
end if;
end if;
end process;
ERSR_Reg(11 downto 6) <= "000000";
-----
D_Error_OutPROC: process(ERSR_Reg, ERSR_Par12_0, ERSR_Par15_13)
begin
D_Error_Out(5 downto 0) <= ERSR_Reg(5 downto 0);
D_Error_Out(11 downto 6) <= "000000";
D_Error_Out(15 downto 12) <= ERSR_Reg(15 downto 12);
D_Error_Out(31 downto 16) <= "0000000000000000";
DPar_Error_Out <= not (ERSR_Par12_0 xor ERSR_Par15_13);
end process;
-----
ParityErrorErrHandl <= (ParityGen(ERSR_Reg(12 downto 0)) xor ERSR_Par12_0) or
(ParityGen(ERSR_Reg(15 downto 13)) xor ERSR_Par15_13);
-------------------------------------------------
-- Processes that generates the output signals --
-------------------------------------------------
Errors_ERSR <= ERSR_Shadow and not(EMR_Reg);
Errors <= ERSR_Tmp and not(EMR_Reg);
MaskedErrors_ERSR <= ERSR_Shadow and EMR_Reg;
MaskedErrors <= ERSR_Tmp and EMR_Reg;
-----
ErrHand: process
begin
wait until Clk_Int'event and Clk_Int = '0';
Int_MaskErr_fck <= Vector_OR(MaskedErrors) or Vector_OR(MaskedErrors_ERSR);
Errors_Sig(2 downto 0) <= Errors(2 downto 0) or Errors_ERSR(2 downto 0);
Errors_Sig(5 downto 4) <= Errors(5 downto 4) or Errors_ERSR(5 downto 4);
ErrorReset_N <= not (Vector_OR(Errors and ResetOrHalt_N) or
Vector_OR(Errors_ERSR and ResetOrHalt_N));
end process;
Errors_Sig(3) <= '0';
-----
HaltHand: process
begin
wait until Clk_Int'event and Clk_Int = '0';
ErrorHalt_N <= not (Vector_OR(Errors and not (ResetOrHalt_N)) or
Vector_OR(Errors_ERSR and not (ResetOrHalt_N))) ;
end process;
-----
SigClkRis: process(Reset_OUT_N, Clk_Int)
begin
if Reset_OUT_N = '0' then
Int_MaskErr_rck1 <= '0';
Int_MaskErr_rck2 <= '0';
MecHWErr_OUT_N <= '1';
SysErr_OUT_N <= '1';
elsif Clk_Int'event and Clk_Int = '1' then
Int_MaskErr_rck1 <= Int_MaskErr_fck;
Int_MaskErr_rck2 <= Int_MaskErr_rck1;
MecHWErr_OUT_N <= not(ERSR_Shadow(5));
SysErr_OUT_N <= not(Vector_OR(Errors_Sig) and Vector_OR(Errors_ERSR));
end if;
end process;
Int_MaskErr <= Int_MaskErr_rck1 and not Int_MaskErr_rck2;
process(Reset_OUT_N, Clk_Int)
begin
if Reset_OUT_N = '0' then
SysAv_OUT_loc <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
SysAv_OUT_loc <= ERSR_Reg(12) and CPUHalt_OUT_N;
end if;
end process;
SysAv_OUT <= SysAv_OUT_loc and not NoClkDetect;
end Mini_Spec ;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: interrupt handler
-- File name: inthandl.vhd
-- VHDL unit: inT_HANDLER
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity inT_HANDLER is
port (
Clk_Int : in std_logic;
MHold_Out_ck1_N : in Std_Logic;
D_Int_In : in std_logic_Vector(31 downto 0);
DPar_Int_In : in std_logic;
Reset_Int_N : in std_logic;
Reset_Out_N : in std_logic;
IntShapeReg_N : in std_logic;
IntPendReg_N : in std_logic;
IntMaskReg_N : in std_logic;
IntClearReg_N : in std_logic;
IntForceReg_N : in std_logic;
Wr_Int_N : in std_logic;
ExtInt_In_fck : in std_logic_vector(4 downto 0);
ExtInt_In_rck : in std_logic_vector(4 downto 0);
IntAck_In : in std_logic;
A_Int_Trap : in std_logic_vector(3 downto 0);
In_Int : in std_logic_vector(9 downto 0);
IntrTest_En : in std_logic;
ErrResStatReg_N : in std_logic;
D_Error_Out : in std_logic_Vector(31 downto 0);
DPar_Error_Out : in std_logic;
SysFSReg_N : in std_logic;
D_Fault_Out : in std_logic_Vector(31 downto 0);
DPar_Fault_Out : in std_logic;
ParityErrorErrHandl : in std_logic;
ParityErrorFault : in std_logic;
ParityErrorWDog : in std_logic;
AnyInterrupt : out std_logic;
ExtIntAck_Out : out std_logic;
IRL_Out : out std_logic_vector(3 downto 0);
ParityErrorIntErr : out std_logic;
D_IntErr_Out : out std_logic_Vector(31 downto 0);
DPar_IntErr_out : out std_logic
);
end inT_HANDLER;
architecture Mini_Spec of inT_HANDLER is
------------------------------------------------------------------------
---- Function declarations -----------------
-----------------------------------------------------------------------
function BitValOfIFR(IFR_Reg : std_logic_vector;
IRL_AckNr : std_logic_vector
) return std_logic is
variable Res : std_logic;
variable IRL_AckNr_LOC : std_logic_vector(3 downto 0);
begin
IRL_AckNr_LOC(3 downto 0) := IRL_AckNr(3 downto 0);
case IRL_AckNr_LOC(3 downto 0) is
when "1111" => Res := IFR_Reg(15);
when "1110" => Res := IFR_Reg(14);
when "1101" => Res := IFR_Reg(13);
when "1100" => Res := IFR_Reg(12);
when "1011" => Res := IFR_Reg(11);
when "1010" => Res := IFR_Reg(10);
when "1001" => Res := IFR_Reg(9);
when "1000" => Res := IFR_Reg(8);
when "0111" => Res := IFR_Reg(7);
when "0110" => Res := IFR_Reg(6);
when "0101" => Res := IFR_Reg(5);
when "0100" => Res := IFR_Reg(4);
when "0011" => Res := IFR_Reg(3);
when "0010" => Res := IFR_Reg(2);
when "0001" => Res := IFR_Reg(1);
when others => Res := '0';
end case;
return Res;
end BitValOfIFR;
signal IRL_loc : std_logic_Vector(3 downto 0);
--- The ISR, IPR, IMR and the IFR register
signal ISR_Reg : std_logic_Vector(15 downto 0);
signal ISR_Par : std_logic;
signal IPR_Reg : std_logic_Vector(15 downto 0);
signal IPR_Reg_Int : std_logic_Vector(15 downto 1);
signal IPR_Par : std_logic;
signal IMR_Reg : std_logic_Vector(15 downto 0);
signal IMR_Par : std_logic;
signal IFR_Reg : std_logic_Vector(15 downto 0);
signal IFR_Par : std_logic;
signal IPR_Reg_Din : std_logic_Vector(15 downto 1);
signal IPRClear : Std_Logic_Vector(15 downto 1);
signal ICR_Reg : Std_Logic_Vector(15 downto 1);
signal ICRrck : Std_Logic_Vector(15 downto 1);
signal ExtIntDirty : std_logic_vector(4 downto 0);
signal ExtIntClean : Std_Logic_Vector(4 downto 0);
signal ExtInt_High : Std_Logic_Vector(4 downto 0);
signal ExtInt_High_rck : Std_Logic_Vector(4 downto 0);
signal ExtInt_PULS : Std_Logic_Vector(4 downto 0);
signal IRL_AckNr : Std_Logic_Vector(3 downto 0);
signal IntAck_Int_rck : Std_Logic;
signal ICRAdvReset : Std_Logic;
signal ExtIntAckQual1 : Std_Logic_Vector(6 downto 0);
signal ExtIntAckQual2_2 : Std_Logic;
signal ExtIntAckQual2_3 : Std_Logic;
signal ExtIntAckQual2_10 : Std_Logic;
signal ExtIntAckQual2_11 : Std_Logic;
signal ExtIntAckQual2_14 : Std_Logic;
signal ExtIntAck_Out_loc : Std_Logic;
signal IPRRstEn : Std_Logic;
begin
-----
Glitch: process(Clk_Int)
begin
if (Clk_Int'event and Clk_Int = '0') then
ExtIntDirty <= ExtInt_In_fck;
end if;
end process;
-----
Glitch_bis: process(Clk_Int)
begin
if (Clk_Int'event and Clk_Int = '1') then
if ExtInt_In_rck(0) = ExtIntDirty(0) then
ExtIntClean(0) <= ExtIntDirty(0);
end if;
if ExtInt_In_rck(1) = ExtIntDirty(1) then
ExtIntClean(1) <= ExtIntDirty(1);
end if;
if ExtInt_In_rck(2) = ExtIntDirty(2) then
ExtIntClean(2) <= ExtIntDirty(2);
end if;
if ExtInt_In_rck(3) = ExtIntDirty(3) then
ExtIntClean(3) <= ExtIntDirty(3);
end if;
if ExtInt_In_rck(4) = ExtIntDirty(4) then
ExtIntClean(4) <= ExtIntDirty(4);
end if;
end if;
end process;
----------------------------------------------------------------------------
A_Int_Trap_Smpl: process
begin
wait until (Clk_Int'event and Clk_Int = '1');
if IPRRstEn = '1' then
IRL_AckNr <= A_Int_Trap;
else
IRL_AckNr <= "0000";
end if;
IntAck_Int_rck <= IntAck_In and MHold_Out_ck1_N;
end process;
IPRRstEn_Gen: process(IntAck_In, IntAck_Int_rck, MHold_Out_ck1_N)
begin
if IntAck_In = '1' and IntAck_Int_rck = '0' and MHold_Out_ck1_N = '1' then
IPRRstEn <= '1';
else
IPRRstEn <= '0';
end if;
end process;
----------------------------------------------------------------------------
Regs_ISR_IMR: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N = '0' then -- Reset Registers
ISR_Reg(12 downto 0) <= "0000000000000";
ISR_Par <= '1';
IMR_Reg(14 downto 1) <= "11111111111111";
IMR_Par <= '1';
elsif Clk_Int'event and Clk_Int = '0' then
-- ISR
if IntShapeReg_N = '0' and Wr_Int_N = '0' then -- Write to ISR
ISR_Reg(12 downto 0) <= D_Int_In(12 downto 0);
ISR_Par <= DPar_Int_In;
end if;
-- IMR
if IntMaskReg_N = '0' and Wr_Int_N = '0' then -- Write to IMR
IMR_Reg(14 downto 1) <= D_Int_In(14 downto 1);
IMR_Par <= DPar_Int_In;
end if;
end if;
end process;
----------------------------------------------------------------------------
IFR_Hdling: process(Reset_Int_N, Clk_Int)
variable Tmp : std_logic;
begin
if Reset_Int_N = '0' then
IFR_Reg(15 downto 1) <= "000000000000000";
IFR_Par <= '1';
elsif Clk_Int'event and Clk_Int = '0' then
if IRL_AckNr /= "0000" then
Tmp := BitValOfIFR(IFR_Reg, IRL_AckNr);
if IntrTest_En = '1' and Tmp = '1' then
case IRL_AckNr is
when "1111" => IFR_Reg(15) <= '0';
IFR_Par <= not(IFR_Par);
when "1110" => IFR_Reg(14) <= '0';
IFR_Par <= not(IFR_Par);
when "1101" => IFR_Reg(13) <= '0';
IFR_Par <= not(IFR_Par);
when "1100" => IFR_Reg(12) <= '0';
IFR_Par <= not(IFR_Par);
when "1011" => IFR_Reg(11) <= '0';
IFR_Par <= not(IFR_Par);
when "1010" => IFR_Reg(10) <= '0';
IFR_Par <= not(IFR_Par);
when "1001" => IFR_Reg(9) <= '0';
IFR_Par <= not(IFR_Par);
when "1000" => IFR_Reg(8) <= '0';
IFR_Par <= not(IFR_Par);
when "0111" => IFR_Reg(7) <= '0';
IFR_Par <= not(IFR_Par);
when "0110" => IFR_Reg(6) <= '0';
IFR_Par <= not(IFR_Par);
when "0101" => IFR_Reg(5) <= '0';
IFR_Par <= not(IFR_Par);
when "0100" => IFR_Reg(4) <= '0';
IFR_Par <= not(IFR_Par);
when "0011" => IFR_Reg(3) <= '0';
IFR_Par <= not(IFR_Par);
when "0010" => IFR_Reg(2) <= '0';
IFR_Par <= not(IFR_Par);
when "0001" => IFR_Reg(1) <= '0';
IFR_Par <= not(IFR_Par);
when others => NULL;
end case;
end if;
elsif Wr_Int_N = '0' then
if IntForceReg_N = '0' then
IFR_Reg(15 downto 1) <= D_Int_In(15 downto 1);
IFR_Par <= DPar_Int_In;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
ICR_Hdling1: process(Clk_Int, Reset_Int_N)
begin
if Reset_Int_N = '0' then
ICR_Reg <= "000000000000000";
elsif Clk_Int'event and Clk_Int = '0' then
if Wr_Int_N = '0' and IntClearReg_N = '0' then
ICR_Reg <= D_Int_In(15 downto 1);
elsif ICRAdvReset = '1' then
ICR_Reg <= "000000000000000";
end if;
end if;
end process;
ICR_Hdling2: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N = '0' then
ICRAdvReset <= '0';
elsif Clk_Int'event and Clk_Int = '0' then
if Wr_Int_N = '0' and IntClearReg_N = '0' then
ICRAdvReset <= '1';
else
ICRAdvReset <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------
ICR_Sync: process
begin
wait until Clk_Int'event and Clk_Int = '1';
ICRrck <= ICR_Reg;
end process;
----------------------------------------------------------------------------
IPRClear_Hdling: process(IRL_AckNr)
begin
if IRL_AckNr /= "0000" then
IPRClear <= (others => '0');
case IRL_AckNr is
when "1111" => IPRClear(15) <= '1';
when "1110" => IPRClear(14) <= '1';
when "1101" => IPRClear(13) <= '1';
when "1100" => IPRClear(12) <= '1';
when "1011" => IPRClear(11) <= '1';
when "1010" => IPRClear(10) <= '1';
when "1001" => IPRClear(9) <= '1';
when "1000" => IPRClear(8) <= '1';
when "0111" => IPRClear(7) <= '1';
when "0110" => IPRClear(6) <= '1';
when "0101" => IPRClear(5) <= '1';
when "0100" => IPRClear(4) <= '1';
when "0011" => IPRClear(3) <= '1';
when "0010" => IPRClear(2) <= '1';
when "0001" => IPRClear(1) <= '1';
when others => NULL;
end case;
else
IPRClear <= (others => '0');
end if;
end process;
----------------------------------------------------------------------------
ISR_Reg(13) <= '0';
ISR_Reg(14) <= '0';
ISR_Reg(15) <= '0';
IPR_Reg(0) <= '0';
IMR_Reg(0) <= '0';
IMR_Reg(15) <= '0';
IFR_Reg(0) <= '0';
IntHdl_Mux: process(IntShapeReg_N, ISR_Reg, ISR_Par,
IntPendReg_N, IPR_Reg, IPR_Par,
IntMaskReg_N, IMR_Reg, IMR_Par,
IntForceReg_N, IFR_Reg, IFR_Par,
ErrResStatReg_N, D_Error_Out, DPar_Error_Out,
SysFSReg_N, D_Fault_Out, DPar_Fault_Out)
begin
for i in 0 to 1 loop
D_IntErr_Out(i) <= (ISR_Reg(i) and not IntShapeReg_N) or
(IPR_Reg(i) and not IntPendReg_N) or
(IMR_Reg(i) and not IntMaskReg_N) or
(IFR_Reg(i) and not IntForceReg_N) or
(D_Error_Out(i) and not ErrResStatReg_N);
end loop;
for i in 2 to 5 loop
D_IntErr_Out(i) <= (ISR_Reg(i) and not IntShapeReg_N) or
(IPR_Reg(i) and not IntPendReg_N) or
(IMR_Reg(i) and not IntMaskReg_N) or
(IFR_Reg(i) and not IntForceReg_N) or
(D_Error_Out(i) and not ErrResStatReg_N) or
(D_Fault_Out(i) and not SysFSReg_N);
end loop;
for i in 6 to 11 loop
D_IntErr_Out(i) <= (ISR_Reg(i) and not IntShapeReg_N) or
(IPR_Reg(i) and not IntPendReg_N) or
(IMR_Reg(i) and not IntMaskReg_N) or
(IFR_Reg(i) and not IntForceReg_N) or
(D_Fault_Out(i) and not SysFSReg_N);
end loop;
for i in 12 to 15 loop
D_IntErr_Out(i) <= (ISR_Reg(i) and not IntShapeReg_N) or
(IPR_Reg(i) and not IntPendReg_N) or
(IMR_Reg(i) and not IntMaskReg_N) or
(IFR_Reg(i) and not IntForceReg_N) or
(D_Error_Out(i) and not ErrResStatReg_N) or
(D_Fault_Out(i) and not SysFSReg_N);
end loop;
DPar_IntErr_Out <= (ISR_Par and not IntShapeReg_N) or
(IPR_Par and not IntPendReg_N) or
(IMR_Par and not IntMaskReg_N) or
(IFR_Par and not IntForceReg_N) or
(DPar_Error_Out and not ErrResStatReg_N) or
(DPar_Fault_Out and not SysFSReg_N);
end process;
D_IntErr_Out(31 downto 16) <= "0000000000000000";
----------------------------------------------------------------------------
ParityError_Or: process(ParityErrorErrHandl, ParityErrorFault,
ParityErrorWDog,
ISR_Reg, ISR_Par,
IMR_Reg, IMR_Par,
IFR_Reg, IFR_Par)
begin
ParityErrorIntErr <= ParityErrorErrHandl or ParityErrorFault or
ParityErrorWDog or
(ParityGen(ISR_Reg) xor ISR_Par) or
(ParityGen(IMR_Reg) xor IMR_Par) or
(ParityGen(IFR_Reg) xor IFR_Par);
end process;
----------------------------------------------------------------------------
ExtIntAckQual1 <= IRL_AckNr & ISR_Reg(7 downto 5);
ExtIntAckQual2_2 <= (not(IntrTest_En and IFR_Reg(2))) ;
ExtIntAckQual2_3 <= (not(IntrTest_En and IFR_Reg(3))) ;
ExtIntAckQual2_10 <= (not(IntrTest_En and IFR_Reg(10))) ;
ExtIntAckQual2_11 <= (not(IntrTest_En and IFR_Reg(11))) ;
ExtIntAckQual2_14 <= (not(IntrTest_En and IFR_Reg(14))) ;
ExtIntAck_Out_PROC: process(ExtIntAckQual1,
ExtIntAckQual2_2, ExtIntAckQual2_3,
ExtIntAckQual2_10, ExtIntAckQual2_11, ExtIntAckQual2_14)
begin
case ExtIntAckQual1 is
when "0010001" =>
ExtIntAck_Out_loc <= ExtIntAckQual2_2;
when "0011010" =>
ExtIntAck_Out_loc <= ExtIntAckQual2_3;
when "1010011" =>
ExtIntAck_Out_loc <= ExtIntAckQual2_10;
when "1011100" =>
ExtIntAck_Out_loc <= ExtIntAckQual2_11;
when "1110101" =>
ExtIntAck_Out_loc <= ExtIntAckQual2_14;
when others =>
ExtIntAck_Out_loc <= '0';
end case;
end process;
Delayprocess: process(Clk_Int, Reset_Out_N)
begin
if Reset_Out_N = '0' then
ExtIntAck_Out <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
ExtIntAck_Out <= ExtIntAck_Out_loc;
end if;
end process;
-----------------------------------------------------------
-- Processes that process the external interrupt signals --
-----------------------------------------------------------
ExtInt_High(4) <= not(ExtIntClean(4) xor ISR_Reg(12));
ExtInt_High(3) <= not(ExtIntClean(3) xor ISR_Reg(11));
ExtInt_High(2) <= not(ExtIntClean(2) xor ISR_Reg(10));
ExtInt_High(1) <= not(ExtIntClean(1) xor ISR_Reg(9));
ExtInt_High(0) <= not(ExtIntClean(0) xor ISR_Reg(8));
-----
ExtInt_HighSmpling: process
begin
wait until Clk_Int'event and Clk_Int = '1';
ExtInt_High_rck(4) <= ExtInt_High(4) or not ISR_Reg(4);
ExtInt_High_rck(3) <= ExtInt_High(3) or not ISR_Reg(3);
ExtInt_High_rck(2) <= ExtInt_High(2) or not ISR_Reg(2);
ExtInt_High_rck(1) <= ExtInt_High(1) or not ISR_Reg(1);
ExtInt_High_rck(0) <= ExtInt_High(0) or not ISR_Reg(0);
end process;
----- pulses detecting rising edge of signals ExtInt_High(*)
-- No pulse is generated when level triggered interruptions
ExtInt_PULS(4) <= ExtInt_High(4) and not(ExtInt_High_rck(4));
ExtInt_PULS(3) <= ExtInt_High(3) and not(ExtInt_High_rck(3));
ExtInt_PULS(2) <= ExtInt_High(2) and not(ExtInt_High_rck(2));
ExtInt_PULS(1) <= ExtInt_High(1) and not(ExtInt_High_rck(1));
ExtInt_PULS(0) <= ExtInt_High(0) and not(ExtInt_High_rck(0));
----- D inputs of IPR DFFs.
IPR_Reg_Din(1) <= '0' when ((IPRClear(1) = '1' and IFR_Reg(1) = '0' and IntrTest_En = '1') or
(IPRClear(1) = '1' and IntrTest_En = '0')) and In_Int(0) = '0' else
'0' when ICR_Reg(1) = '1' and In_Int(0) = '0' else
IPR_Reg_Int(1) or In_Int(0);
IPR_Reg_Din(2) <= '0' when ((IPRClear(2) = '1' and IFR_Reg(2) = '0' and IntrTest_En = '1') or
(IPRClear(2) = '1' and IntrTest_En = '0')) and
((ExtInt_PULS(0) = '0' and ISR_Reg(0) = '1')) else
'0' when ICR_Reg(2) = '1' and (ExtInt_PULS(0) = '0' and ISR_Reg(0) = '1') else
IPR_Reg_Int(2) or ExtInt_PULS(0);
IPR_Reg_Din(3) <= '0' when ((IPRClear(3) = '1' and IFR_Reg(3) = '0' and IntrTest_En = '1') or
(IPRClear(3) = '1' and IntrTest_En = '0')) and
((ExtInt_PULS(1) = '0' and ISR_Reg(1) = '1')) else
'0' when ICR_Reg(3) = '1' and (ExtInt_PULS(1) = '0' and ISR_Reg(1) = '1') else
IPR_Reg_Int(3) or ExtInt_PULS(1);
IPR_Reg_Din(4) <= '0' when ((IPRClear(4) = '1' and IFR_Reg(4) = '0' and IntrTest_En = '1') or
(IPRClear(4) = '1' and IntrTest_En = '0')) and In_Int(1) = '0' else
'0' when ICR_Reg(4) = '1' and In_Int(1) = '0' else
IPR_Reg_Int(4) or In_Int(1);
IPR_Reg_Din(5) <= '0' when ((IPRClear(5) = '1' and IFR_Reg(5) = '0' and IntrTest_En = '1') or
(IPRClear(5) = '1' and IntrTest_En = '0')) and In_Int(2) = '0' else
'0' when ICR_Reg(5) = '1' and In_Int(2) = '0' else
IPR_Reg_Int(5) or In_Int(2);
IPR_Reg_Din(6) <= '0' when ((IPRClear(6) = '1' and IFR_Reg(6) = '0' and IntrTest_En = '1') or
(IPRClear(6) = '1' and IntrTest_En = '0')) and In_Int(3) = '0' else
'0' when ICR_Reg(6) = '1' and In_Int(3) = '0' else
IPR_Reg_Int(6) or In_Int(3);
IPR_Reg_Din(7) <= '0' when ((IPRClear(7) = '1' and IFR_Reg(7) = '0' and IntrTest_En = '1') or
(IPRClear(7) = '1' and IntrTest_En = '0')) and In_Int(4) = '0' else
'0' when ICR_Reg(7) = '1' and In_Int(4) = '0' else
IPR_Reg_Int(7) or In_Int(4);
IPR_Reg_Din(8) <= '0' when ((IPRClear(8) = '1' and IFR_Reg(8) = '0' and IntrTest_En = '1') or
(IPRClear(8) = '1' and IntrTest_En = '0')) and
(In_Int(5)) = '0' else
'0' when ICR_Reg(8) = '1' and (In_Int(5)) = '0' else
IPR_Reg_Int(8) or (In_Int(5));
IPR_Reg_Din(9) <= '0' when ((IPRClear(9) = '1' and IFR_Reg(9) = '0' and IntrTest_En = '1') or
(IPRClear(9) = '1' and IntrTest_En = '0')) and In_Int(6) = '0' else
'0' when ICR_Reg(9) = '1' and In_Int(6) = '0' else
IPR_Reg_Int(9) or In_Int(6);
IPR_Reg_Din(10) <= '0' when ((IPRClear(10) = '1' and IFR_Reg(10) = '0' and IntrTest_En = '1') or
(IPRClear(10) = '1' and IntrTest_En = '0')) and
((ExtInt_PULS(2) = '0' and ISR_Reg(2) = '1')) else
'0' when ICR_Reg(10) = '1' and (ExtInt_PULS(2) = '0' and ISR_Reg(2) = '1') else
IPR_Reg_Int(10) or ExtInt_PULS(2);
IPR_Reg_Din(11) <= '0' when ((IPRClear(11) = '1' and IFR_Reg(11) = '0' and IntrTest_En = '1') or
(IPRClear(11) = '1' and IntrTest_En = '0')) and
((ExtInt_PULS(3) = '0' and ISR_Reg(3) = '1')) else
'0' when ICR_Reg(11) = '1' and (ExtInt_PULS(3) = '0' and ISR_Reg(3) = '1') else
IPR_Reg_Int(11) or ExtInt_PULS(3);
IPR_Reg_Din(12) <= '0' when ((IPRClear(12) = '1' and IFR_Reg(12) = '0' and IntrTest_En = '1') or
(IPRClear(12) = '1' and IntrTest_En = '0')) and In_Int(7) = '0' else
'0' when ICR_Reg(12) = '1' and In_Int(7) = '0' else
IPR_Reg_Int(12) or In_Int(7);
IPR_Reg_Din(13) <= '0' when ((IPRClear(13) = '1' and IFR_Reg(13) = '0' and IntrTest_En = '1') or
(IPRClear(13) = '1' and IntrTest_En = '0')) and In_Int(8) = '0' else
'0' when ICR_Reg(13) = '1' and In_Int(8) = '0' else
IPR_Reg_Int(13) or In_Int(8);
IPR_Reg_Din(14) <= '0' when ((IPRClear(14) = '1' and IFR_Reg(14) = '0' and IntrTest_En = '1') or
(IPRClear(14) = '1' and IntrTest_En = '0')) and
((ExtInt_PULS(4) = '0' and ISR_Reg(4) = '1')) else
'0' when ICR_Reg(14) = '1' and (ExtInt_PULS(4) = '0' and ISR_Reg(4) = '1') else
IPR_Reg(14) or ExtInt_PULS(4);
IPR_Reg_Din(15) <= '0' when ((IPRClear(15) = '1' and IFR_Reg(15) = '0' and IntrTest_En = '1') or
(IPRClear(15) = '1' and IntrTest_En = '0')) and In_Int(9) = '0' else
'0' when ICR_Reg(15) = '1' and In_Int(9) = '0' else
IPR_Reg_Int(15) or In_Int(9);
-----
IPR_Intprocess: process(Clk_Int, Reset_Out_N)
begin
if Reset_Out_N = '0' then
IPR_Reg_Int(15 downto 1) <= "000000000000000";
elsif Clk_Int'event and Clk_Int = '1' then
IPR_Reg_Int(15 downto 1) <= IPR_Reg_Din(15 downto 1);
end if;
end process;
IPR_process: process(IPR_Reg_Int, ISR_Reg, ExtInt_High)
begin
IPR_Reg(1) <= IPR_Reg_Int(1);
if ISR_Reg(0) = '0' then
IPR_Reg(2) <= ExtInt_High(0);
else
IPR_Reg(2) <= IPR_Reg_Int(2);
end if;
if ISR_Reg(1) = '0' then
IPR_Reg(3) <= ExtInt_High(1);
else
IPR_Reg(3) <= IPR_Reg_Int(3);
end if;
IPR_Reg(9 downto 4) <= IPR_Reg_Int(9 downto 4);
if ISR_Reg(2) = '0' then
IPR_Reg(10) <= ExtInt_High(2);
else
IPR_Reg(10) <= IPR_Reg_Int(10);
end if;
if ISR_Reg(3) = '0' then
IPR_Reg(11) <= ExtInt_High(3);
else
IPR_Reg(11) <= IPR_Reg_Int(11);
end if;
IPR_Reg(13 downto 12) <= IPR_Reg_Int(13 downto 12);
if ISR_Reg(4) = '0' then
IPR_Reg(14) <= ExtInt_High(4);
else
IPR_Reg(14) <= IPR_Reg_Int(14);
end if;
IPR_Reg(15) <= IPR_Reg_Int(15);
end process;
IPR_Par <= ParityGen(IPR_Reg);
--------------------------------------------------------
-- Process that controls which IRL line to be active ---
--------------------------------------------------------
OUT_process: process(Reset_Out_N, Clk_Int)
variable int_active : std_logic_vector(15 downto 1);
variable int_masked : std_logic_vector(15 downto 1);
begin
if Reset_Out_N = '0' then
AnyInterrupt <= '0';
IRL_loc <= "0000";
elsif Clk_Int'event and Clk_Int = '0' then
if IntrTest_En = '1' then
int_active(15 downto 1) := IPR_Reg(15 downto 1) or IFR_Reg(15 downto 1);
else
int_active(15 downto 1) := IPR_Reg(15 downto 1);
end if;
int_masked(1) := int_active(1) and not IMR_Reg(1) and
not (IPRClear(1));
int_masked(2) := int_active(2) and not IMR_Reg(2) and
not (IPRClear(2) and ISR_Reg(0));
int_masked(3) := int_active(3) and not IMR_Reg(3) and
not (IPRClear(3) and ISR_Reg(1));
int_masked(9 downto 4) := int_active(9 downto 4) and not IMR_Reg(9 downto 4) and
not (IPRClear(9 downto 4));
int_masked(10) := int_active(10) and not IMR_Reg(10) and
not (IPRClear(10) and ISR_Reg(2));
int_masked(11) := int_active(11) and not IMR_Reg(11) and
not (IPRClear(11) and ISR_Reg(3));
int_masked(13 downto 12) := int_active(13 downto 12) and not IMR_Reg(13 downto 12) and
not (IPRClear(13 downto 12));
int_masked(14) := int_active(14) and not IMR_Reg(14) and
not (IPRClear(14) and ISR_Reg(4));
int_masked(15) := int_active(15) and not (IPRClear(15));
AnyInterrupt <= Vector_Or(int_masked);
if int_masked(15) = '1' then
IRL_loc <= "1111";
elsif int_masked(14) = '1' then
IRL_loc <= "1110";
elsif int_masked(13) = '1' then
IRL_loc <= "1101";
elsif int_masked(12) = '1' then
IRL_loc <= "1100";
elsif int_masked(11) = '1' then
IRL_loc <= "1011";
elsif int_masked(10) = '1' then
IRL_loc <= "1010";
elsif int_masked(9) = '1' then
IRL_loc <= "1001";
elsif int_masked(8) = '1' then
IRL_loc <= "1000";
elsif int_masked(7) = '1' then
IRL_loc <= "0111";
elsif int_masked(6) = '1' then
IRL_loc <= "0110";
elsif int_masked(5) = '1' then
IRL_loc <= "0101";
elsif int_masked(4) = '1' then
IRL_loc <= "0100";
elsif int_masked(3) = '1' then
IRL_loc <= "0011";
elsif int_masked(2) = '1' then
IRL_loc <= "0010";
elsif int_masked(1) = '1' then
IRL_loc <= "0001";
else
IRL_loc <= "0000";
end if;
end if;
end process;
IRL_Out <= IRL_loc;
end Mini_Spec ;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: watch dog
-- File name: wdog.vhd
-- VHDL unit: WatchDog
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED."-";
entity WatchDog is
port(
Reset_Out_N : in Std_Logic;
Clk_Int : in Std_Logic;
WDClk_In : in Std_Logic;
WDStrobe : in Std_Logic;
Wr_Int_N : in Std_Logic;
WDProgramReg_N : in Std_Logic;
WDTDSetReg_N : in Std_Logic;
D_Int_In : in Std_Logic_Vector(31 downto 0);
DPar_Int_In : in Std_Logic;
D_Wdog_Out : out Std_Logic_Vector(31 downto 0);
DPar_Wdog_Out : out Std_Logic;
WDInterrupt : out Std_Logic;
WDReset_N : out Std_Logic;
ParityErrorWDog : out Std_Logic
);
end WatchDog;
architecture Mini_Spec of WatchDog is
-- type WatchDogControllerType is (WDInit,WDDisabled,WDEnabled,
-- WDResetTimerEnabled,WDHalted);
signal State : Std_Logic_Vector(2 downto 0);
signal StatePar : Std_Logic;
signal D_Wdog_Out_loc : Std_Logic_Vector(31 downto 0);
signal WDProAndTOReg : Std_Logic_Vector(31 downto 0);
signal WDProAndTORegPar : Std_Logic;
signal ScalerCount : Std_Logic_Vector(7 downto 0);
signal CounterCount : Std_Logic_Vector(15 downto 0);
signal LoadCounter : Std_Logic;
signal LoadResetCounter : Std_Logic;
signal WDProgram : Std_Logic;
signal WDProgramReset : Std_Logic;
signal WDProgram_Temp : Std_Logic;
signal WDProgram_ClkWD : Std_Logic;
signal WDTrapDoorSet : Std_Logic;
signal WDTrapDoorSetReset : Std_Logic;
signal WDTrapDoorSet_Temp : Std_Logic;
signal WDTrapDoorSet_ClkWD : Std_Logic;
signal Timeout : Std_Logic;
signal CounterClk : Std_Logic;
signal WDProgramReset_fck : Std_Logic;
signal WDTrapDoorSetReset_fck : Std_Logic;
signal WDInterrupt_ClkWD : Std_Logic;
signal WDInterrupt_fck : Std_Logic;
signal WDInterrupt_rck1 : Std_Logic;
signal WDInterrupt_rck2 : Std_Logic;
signal RstWDMachines_1_N : Std_Logic;
signal RstWDMachines_N : Std_Logic;
signal WDParCheck_fck1 : Std_Logic;
signal WDParCheck_fck : Std_Logic;
begin
-----
fckSync1: process(Reset_Out_N, Clk_Int)
begin
if Reset_Out_N = '0' then
WDParCheck_fck1 <= '0';
WDParCheck_fck <= '0';
elsif Clk_Int'event and Clk_Int = '0' then
WDParCheck_fck1 <= ParityCheck(State, StatePar);
WDParCheck_fck <= WDParCheck_fck1;
end if;
end process;
ParityErrorWDog <= ParityCheck(WDProAndTOReg, WDProAndTORegPar) or
WDParCheck_fck;
-----
WriteRegs: process(Reset_Out_N, Clk_Int)
begin
if Reset_Out_N = '0' then --Reset Registers
WDProAndTOReg <= "11111111111111111111111111111111";
WDProAndTORegPar <= '1';
WDTrapDoorSet <= '0';
WDProgram <= '0';
elsif (Clk_Int'event and Clk_Int = '0') then
if Wr_Int_N = '0' then
--Write Watchdog Program and Timeout Acknowledge Register
if (WDProgramReg_N = '0') then
WDProAndTOReg <= D_Int_In;
WDProAndTORegPar <= DPar_Int_In;
WDProgram <= '1';
--Write Watchdog Trap Door Set
elsif (WDTDSetReg_N = '0') then
WDTrapDoorSet <= '1';
end if;
else -- No write
-- Insure that the signals is valid from Clk- to Clk-
WDTrapDoorSet <= '0';
WDProgram <= '0';
end if;
end if;
end process;
--### Generate reset signal for Watchdog Part
RstWDMachinesGen: process(Reset_Out_N, WDClk_In)
begin
if Reset_Out_N = '0' then
RstWDMachines_1_N <= '0';
RstWDMachines_N <= '0';
elsif WDClk_In'event and WDClk_In = '1' then
if WDStrobe = '1' then
RstWDMachines_1_N <= '1';
RstWDMachines_N <= RstWDMachines_1_N;
end if;
end if;
end process;
-----
fck_sync1:process(Clk_Int, Reset_Out_N)
begin
if Reset_Out_N = '0' then
WDProgramReset_fck <= '0';
WDTrapDoorSetReset_fck <= '0';
elsif Clk_Int'event and Clk_Int = '0' then
WDProgramReset_fck <= WDProgramReset;
WDTrapDoorSetReset_fck <= WDTrapDoorSetReset;
end if;
end process;
----
WDProgram_Sync1:process(Clk_Int, Reset_Out_N)
begin
if Reset_Out_N = '0' then
WDProgram_Temp <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
if WDProgramReset_fck = '1' then
WDProgram_Temp <= '0';
else
WDProgram_Temp <= WDProgram or WDProgram_Temp;
end if;
end if;
end process;
-----
WDProgram_Sync2:process(RstWDMachines_N, WDClk_In)
begin
if RstWDMachines_N = '0' then
WDProgram_ClkWD <= '0';
elsif WDClk_In'event and WDClk_In = '0' then
if WDStrobe = '1' then
WDProgram_ClkWD <= WDProgram_Temp;
end if;
end if;
end process;
-----
WDTrapDoorSet_Sync1: process(Clk_Int, Reset_Out_N)
begin
if Reset_Out_N = '0' then
WDTrapDoorSet_Temp <= '0';
elsif Clk_Int'event and Clk_Int = '1' then
if WDTrapDoorSetReset_fck = '1' then
WDTrapDoorSet_Temp <= '0';
else
WDTrapDoorSet_Temp <= WDTrapDoorSet or WDTrapDoorSet_Temp;
end if;
end if;
end process;
-----
WDTrapDoorSet_Sync2:process(RstWDMachines_N, WDClk_In)
begin
if RstWDMachines_N = '0' then
WDTrapDoorSet_ClkWD <= '0';
elsif WDClk_In'event and WDClk_In = '0' then
if WDStrobe = '1' then
WDTrapDoorSet_ClkWD <= WDTrapDoorSet_Temp;
end if;
end if;
end process;
-----
WatchDogController: process(RstWDMachines_N, WDClk_In)
begin
if RstWDMachines_N = '0' then
State <= "000" ; --WDInit
StatePar <= '1' ; --WDInit
LoadCounter <= '0';
LoadResetCounter <= '0';
WDInterrupt_ClkWD <= '0';
WDReset_N <= '1';
WDProgramReset <= '0';
WDTrapDoorSetReset <= '0';
elsif WDClk_In'event and WDClk_In = '1' then
if WDStrobe = '1' then
LoadCounter <= '0';
LoadResetCounter <= '0';
WDInterrupt_ClkWD <= '0';
WDReset_N <= '1';
WDProgramReset <= '0';
WDTrapDoorSetReset <= '0';
case State is
--WDInit
when "000" =>
--WDEnabled
if (WDProgram_ClkWD = '1') then
State <= "001";
StatePar <= '0';
LoadCounter <= '1';
WDProgramReset <= '1';
--WDDisabled
elsif (WDTrapDoorSet_ClkWD = '1') then
State <= "100";
StatePar <= '0';
WDTrapDoorSetReset <= '1';
--WDResetTimerEnabled
elsif (Timeout = '1') then
State <= "010";
StatePar <= '0';
LoadResetCounter <= '1';
--WDInit
else
State <= "000";
StatePar <= '1';
end if;
--WDDisabled
when "100" =>
--WDEnabled
if (WDProgram_ClkWD = '1') then
State <= "001";
StatePar <= '0';
LoadCounter <= '1';
--WDDisabled
else
State <= "100";
StatePar <= '0';
end if;
--WDEnabled
when "001" =>
--WDResetTimerEnabled
if (Timeout = '1') then
State <= "010";
StatePar <= '0';
LoadResetCounter <= '1';
--WDEnabled
elsif (WDProgram_ClkWD = '1') then
State <= "001";
StatePar <= '0';
LoadCounter <= '1';
WDProgramReset <= '1';
--WDEnabled
else
State <= "001";
StatePar <= '0';
end if;
--WDResetTimerEnabled
when "010" =>
--WDEnabled
if (WDProgram_ClkWD = '1') then
State <= "001";
StatePar <= '0';
LoadCounter <= '1';
WDProgramReset <= '1';
--WDHalted
elsif (Timeout = '1') then
State <= "011";
StatePar <= '1';
--WDResetTimerEnabled
else
State <= "010";
StatePar <= '0';
WDInterrupt_ClkWD <= '1';
end if;
--WDHalted
when "011" =>
--WDHalted
State <= "011";
StatePar <= '1';
WDReset_N <= '0';
when others => -- generate a parity error
State <= "111";
StatePar <= '1';
end case;
end if;
end if;
end process;
-----
Scaler: process(RstWDMachines_N, WDClk_In)
begin
if RstWDMachines_N = '0' then
ScalerCount <= WDProAndTOReg(23 downto 16);
CounterClk <= '0';
elsif WDClk_In'event and WDClk_In = '1' then
if WDStrobe = '1' then
if (LoadCounter = '1') or (LoadResetCounter = '1') then
ScalerCount <= WDProAndTOReg(23 downto 16);
CounterClk <= '0';
else
if (ScalerCount = "00000000") then
ScalerCount <= WDProAndTOReg(23 downto 16);
CounterClk <= '1';
else
ScalerCount <= ScalerCount - 1;
CounterClk <= '0';
end if;
end if;
end if;
end if;
end process;
-----
Counter: process(RstWDMachines_N, WDClk_In)
begin
if RstWDMachines_N = '0' then
CounterCount <= WDProAndTOReg(15 downto 0);
Timeout <= '0';
elsif WDClk_In'event and WDClk_In = '1' then
if WDStrobe = '1' then
-- Synchronous Load
if (LoadCounter = '1') then
CounterCount <= WDProAndTOReg(15 downto 0);
Timeout <= '0';
elsif (LoadResetCounter = '1') then
CounterCount <= "00000000" & WDProAndTOReg(31 downto 24);
Timeout <= '0';
elsif CounterClk = '1' then
if (CounterCount = "0000000000000000") then
Timeout <= '1';
else
Timeout <= '0';
CounterCount <= CounterCount - 1;
end if;
else -- Always assert TimeOut
Timeout <= '0';
end if;
end if;
end if;
end process;
-----
fck_sync2:process(Clk_Int, Reset_Out_N)
begin
if Reset_Out_N = '0' then
WDInterrupt_fck <= '0';
elsif Clk_Int'event and Clk_Int = '0' then
WDInterrupt_fck <= WDInterrupt_ClkWD;
end if;
end process;
rck_sync2:process(Clk_Int, Reset_Out_N)
begin
if Reset_Out_N = '0' then
WDInterrupt_rck1 <= '0';
WDInterrupt_rck2 <= '0';
D_Wdog_Out_loc(23 downto 0) <= "000000000000000000000000";
elsif Clk_Int'event and Clk_Int = '1' then
WDInterrupt_rck1 <= WDInterrupt_fck;
WDInterrupt_rck2 <= WDInterrupt_rck1;
D_Wdog_Out_loc(15 downto 0) <= CounterCount;
D_Wdog_Out_loc(23 downto 16) <= ScalerCount;
end if;
end process;
D_Wdog_Out_loc(31 downto 24) <= "00000000";
D_Wdog_Out <= D_Wdog_Out_loc;
DPar_Wdog_Out <= ParityGen(D_Wdog_Out_loc);
WDInterrupt <= WDInterrupt_rck1 and not WDInterrupt_rck2;
end Mini_Spec ;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title:
-- File name: inTERR.VHD
-- VHDL unit: InterruptAndErrorHandling
-- Purpose and functionality:
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use work.all;
library MECLibrary;
use MECLibrary.all;
entity InterruptAndErrorHandling is
port (
Clk_Int : in std_logic;
Rd_Int_In : in Std_Logic;
MHold_Out_ck1_N : in Std_Logic;
SFSRTmp_UD : in Std_Logic;
WDClk_In : in std_logic;
WDStrobe : in Std_Logic;
NewCycle : in std_logic;
D_Int_In : in std_logic_Vector(31 downto 0);
DPar_Int_In : in std_logic;
WDProgramReg_N : in std_logic;
WDTDSetReg_N : in std_logic;
CPUHalt_OUT_N : in std_logic;
Reset_OUT_N : in std_logic;
Reset_Int_N : in std_logic;
Reset_Cause : in Std_Logic_Vector(1 downto 0);
ResetOutDetect : in std_logic;
NoClkDetect : in std_logic;
ErrResStatReg_N : in std_logic;
Wr_Int_N : in std_logic;
ErrorCtrl : in Std_Logic_Vector(9 downto 0);
IUErr_in_N : in std_logic;
IUHWErr_in_N : in std_logic;
IUCmpErr_in_N : in std_logic;
FPUHWErr_in_N : in std_logic;
FPUCmpErr_in_N : in std_logic;
SysFSReg_N : in std_logic;
Instr_Fetch : in std_logic;
Null_Int_rck : in std_logic;
SysBus_Error : in std_logic;
BusTimeOut : in std_logic;
NCError_ck1 : in std_logic;
Unimpl_Address_Out : in std_logic;
CPED : in std_logic;
Illegal_Address_Out : in std_logic;
MemAccess_Violation_Out : in std_logic;
APar_Error : in std_logic;
DPar_Error_ck1 : in std_logic;
CtlPar_Error : in std_logic;
DMATimeOut : in std_logic;
DMAInPrgs : in std_logic;
Intr_UART_Err : in std_logic;
Intr_UARTA_Data : in std_logic;
Intr_UARTB_Data : in std_logic;
CError_ck1 : in std_logic;
AccessType : in Std_Logic_Vector(3 downto 0);
IntShapeReg_N : in std_logic;
IntPendReg_N : in std_logic;
IntMaskReg_N : in std_logic;
IntClearReg_N : in std_logic;
IntForceReg_N : in std_logic;
ExtInt_In_fck : in std_logic_vector(4 downto 0);
ExtInt_In_rck : in std_logic_vector(4 downto 0);
IntAck_In : in std_logic;
A_Int_Trap : in std_logic_vector(3 downto 0);
RTCTimTO : in std_logic;
GPTimTO_A : in std_logic;
IntrTest_En : in std_logic;
SWHalt_En : in std_logic;
D_Wdog_Out : out Std_Logic_Vector(31 downto 0);
DPar_Wdog_Out : out Std_Logic;
AnyInterrupt : out std_logic;
ExtIntAck_Out : out std_logic;
IRL_Out : out std_logic_vector(3 downto 0);
Write_Inhibit : out std_logic;
MExc_Int : out std_logic;
Load_FFAR_N : out std_logic;
SysErr_OUT_N : out std_logic;
MecHWErr_OUT_N : out std_logic;
WDReset_N : out std_logic;
ErrorReset_N : out std_logic;
ErrorHalt_N : out std_logic;
ParityErrorIntErr : out std_logic;
D_IntErr_Out : out std_logic_Vector(31 downto 0);
DPar_IntErr_OUT : out std_logic;
SysAv_OUT : out std_logic );
end InterruptAndErrorHandling;
architecture Mini_Spec of InterruptAndErrorHandling is
component Fault_Handler
port (
Clk_Int : in Std_Logic;
Rd_Int_In : in Std_Logic;
NewCycle : in Std_Logic;
SFSRTmp_UD : in Std_Logic;
Reset_Int_N : in Std_Logic;
Reset_Out_N : in std_logic;
SysFSReg_N : in Std_Logic;
Wr_Int_N : in Std_Logic;
Instr_Fetch : in Std_Logic;
Null_Int_rck : in Std_Logic;
SysBus_Error : in Std_Logic;
BusTimeOut : in Std_Logic;
NCError_ck1 : in Std_Logic;
Unimpl_Address_Out : in Std_Logic;
Illegal_Address_Out : in Std_Logic;
MemAccess_Violation_Out : in Std_Logic;
APar_Error : in Std_Logic;
DPar_Error_ck1 : in Std_Logic;
CtlPar_Error : in Std_Logic;
DMATimeOut : in Std_Logic;
DMAInPrgs : in Std_Logic;
Intr_UART_Err : in Std_Logic;
CError_ck1 : in Std_Logic;
CError_g_rck : out Std_Logic;
WDInterrupt : in Std_Logic;
AccessType : in Std_Logic_Vector(3 downto 0);
Load_FFAR_N : out Std_Logic;
D_Fault_Out : out std_logic_Vector(31 downto 0);
DPar_Fault_Out : out Std_Logic;
ParityErrorFault : out Std_Logic;
Intr_DMAAcc : buffer Std_Logic;
MExc_Int : out Std_Logic;
Write_Inhibit : out Std_Logic
);
end component;
component WatchDog
port(
Reset_Out_N : in std_logic;
Clk_Int : in std_logic;
WDClk_In : in std_logic;
WDStrobe : in Std_Logic;
Wr_Int_N : in std_logic;
WDProgramReg_N : in std_logic;
WDTDSetReg_N : in std_logic;
D_Int_In : in Std_Logic_Vector(31 downto 0);
DPar_Int_In : in std_logic;
D_Wdog_Out : out Std_Logic_Vector(31 downto 0);
DPar_Wdog_Out : out Std_Logic;
WDInterrupt : out std_logic;
WDReset_N : out std_logic;
ParityErrorWDog: out std_logic
);
end component;
component inT_HANDLER
port (
Clk_Int : in std_logic;
MHold_Out_ck1_N : in Std_Logic;
D_Int_In : in std_logic_Vector(31 downto 0);
DPar_Int_In : in std_logic;
Reset_Int_N : in std_logic;
Reset_Out_N : in std_logic;
IntShapeReg_N : in std_logic;
IntPendReg_N : in std_logic;
IntMaskReg_N : in std_logic;
IntClearReg_N : in std_logic;
IntForceReg_N : in std_logic;
Wr_Int_N : in std_logic;
ExtInt_In_fck : in std_logic_vector(4 downto 0);
ExtInt_In_rck : in std_logic_vector(4 downto 0);
IntAck_In : in std_logic;
A_Int_Trap : in std_logic_vector(3 downto 0);
In_Int : in std_logic_vector(9 downto 0);
IntrTest_En : in std_logic;
ErrResStatReg_N : in std_logic;
D_Error_Out : in std_logic_Vector(31 downto 0);
DPar_Error_Out : in std_logic;
SysFSReg_N : in std_logic;
D_Fault_Out : in std_logic_Vector(31 downto 0);
DPar_Fault_Out : in std_logic;
ParityErrorErrHandl : in std_logic;
ParityErrorFault : in std_logic;
ParityErrorWDog : in std_logic;
AnyInterrupt : out std_logic;
ExtIntAck_Out : out std_logic;
IRL_Out : out std_logic_vector(3 downto 0);
ParityErrorIntErr : out std_logic;
D_IntErr_Out : out std_logic_Vector(31 downto 0);
DPar_IntErr_out : out std_logic
);
end component;
component Error_Handler
port (
Clk_Int : in std_logic;
D_Int_In : in std_logic_Vector(31 downto 0);
DPar_Int_In : in std_logic;
CPUHalt_OUT_N : in std_logic;
Reset_OUT_N : in std_logic;
Reset_Cause : in Std_Logic_Vector(1 downto 0);
ResetOutDetect : in Std_Logic;
NoClkDetect : in Std_Logic;
ErrResStatReg_N : in std_logic;
Wr_Int_N : in std_logic;
ErrorCtrl : in Std_Logic_Vector(9 downto 0);
IUErr_in_N : in std_logic;
IUHWErr_in_N : in std_logic;
IUCmpErr_in_N : in std_logic;
FPUHWErr_in_N : in std_logic;
FPUCmpErr_in_N : in std_logic;
MecHWErr_Int_N : in std_logic;
SWHalt_En : in std_logic;
SysErr_OUT_N : out std_logic;
MecHWErr_OUT_N : out std_logic;
ErrorReset_N : out std_logic;
ErrorHalt_N : out std_logic;
D_Error_Out : out std_logic_Vector(31 downto 0);
DPar_Error_Out : out std_logic;
SysAv_OUT : out std_logic;
Int_MaskErr : out std_logic;
ParityErrorErrHandl : out std_logic
);
end component;
signal ParityErrorWDog : std_logic;
signal WDInterrupt : std_logic;
signal D_IntHandl_Out : Std_Logic_Vector(31 downto 0);
signal DPar_IntHandl_Out : std_logic;
signal ParityErrorIntHandl : std_logic;
signal D_Fault_Out : Std_Logic_Vector(31 downto 0);
signal DPar_Fault_Out : std_logic;
signal ParityErrorFault : std_logic;
signal D_Error_Out : std_Logic_Vector(31 downto 0);
signal DPar_Error_Out : std_logic;
signal Int_MaskErr : std_logic;
signal ParityErrorErrHandl : std_logic;
signal Intr_DMAAcc : std_logic;
signal CError_g_rck : std_logic;
signal MECHWErr_In_N : std_logic;
begin
MECHWErr_In_N <= not CPED;
Fault_Handler_1 : Fault_Handler
port map (
Clk_Int => Clk_Int,
Rd_Int_In => Rd_Int_In,
NewCycle => NewCycle,
SFSRTmp_UD => SFSRTmp_UD,
Reset_Int_N => Reset_Int_N,
Reset_Out_N => Reset_Out_N,
SysFSReg_N => SysFSReg_N,
Wr_Int_N => Wr_Int_N,
Instr_Fetch => Instr_Fetch,
Null_Int_rck => Null_Int_rck,
SysBus_Error => SysBus_Error,
BusTimeOut => BusTimeOut,
NCError_ck1 => NCError_ck1,
Unimpl_Address_Out => Unimpl_Address_Out,
Illegal_Address_Out => Illegal_Address_Out,
MemAccess_Violation_Out => MemAccess_Violation_Out,
APar_Error => APar_Error,
DPar_Error_ck1 => DPar_Error_ck1,
CtlPar_Error => CtlPar_Error,
DMATimeOut => DMATimeOut,
DMAInPrgs => DMAInPrgs,
Intr_UART_Err => Intr_UART_Err,
CError_ck1 => CError_ck1,
CError_g_rck => CError_g_rck,
WDInterrupt => WDInterrupt,
AccessType => AccessType,
Load_FFAR_N => Load_FFAR_N,
D_Fault_Out => D_Fault_Out,
DPar_Fault_Out => DPar_Fault_Out,
ParityErrorFault => ParityErrorFault,
Intr_DMAAcc => Intr_DMAAcc,
MExc_Int => MExc_Int,
Write_Inhibit => Write_Inhibit
);
WatchDog_1 : WatchDog
port map (
Reset_Out_N => Reset_Out_N,
Clk_Int => Clk_Int,
WDClk_In => WDClk_In,
WDStrobe => WDStrobe,
Wr_Int_N => Wr_Int_N,
WDProgramReg_N => WDProgramReg_N,
WDTDSetReg_N => WDTDSetReg_N,
D_Int_In => D_Int_In,
DPar_Int_In => DPar_Int_In,
D_Wdog_Out => D_Wdog_Out,
DPar_Wdog_Out => DPar_Wdog_Out,
WDInterrupt => WDInterrupt,
WDReset_N => WDReset_N,
ParityErrorWDog => ParityErrorWDog
);
inT_HANDLER_1 : inT_HANDLER
port map (
Clk_Int => Clk_Int,
MHold_Out_ck1_N => MHold_Out_ck1_N,
D_Int_In => D_Int_In,
DPar_Int_In => DPar_Int_In,
Reset_Int_N => Reset_Int_N,
Reset_Out_N => Reset_Out_N,
IntShapeReg_N => IntShapeReg_N,
IntPendReg_N => IntPendReg_N,
IntMaskReg_N => IntMaskReg_N,
IntClearReg_N => IntClearReg_N,
IntForceReg_N => IntForceReg_N,
Wr_Int_N => Wr_Int_N,
ExtInt_In_fck => ExtInt_In_fck,
ExtInt_In_rck => ExtInt_In_rck,
IntAck_In => IntAck_In,
A_Int_Trap => A_Int_Trap,
In_Int(9) => WDInterrupt,
In_Int(8) => RTCTimTO,
In_Int(7) => GPTimTO_A,
In_Int(6) => DMATimeOut,
In_Int(5) => Intr_DMAAcc,
In_Int(4) => Intr_UART_Err,
In_Int(3) => CError_g_rck,
In_Int(2) => Intr_UARTB_Data,
In_Int(1) => Intr_UARTA_Data,
In_Int(0) => Int_MaskErr,
IntrTest_En => IntrTest_En,
ErrResStatReg_N => ErrResStatReg_N,
D_Error_Out => D_Error_Out,
DPar_Error_Out => DPar_Error_Out,
SysFSReg_N => SysFSReg_N,
D_Fault_Out => D_Fault_Out,
DPar_Fault_Out => DPar_Fault_Out,
ParityErrorErrHandl => ParityErrorErrHandl,
ParityErrorFault => ParityErrorFault,
ParityErrorWDog => ParityErrorWDog,
AnyInterrupt => AnyInterrupt,
ExtIntAck_Out => ExtIntAck_Out,
IRL_Out => IRL_Out,
ParityErrorIntErr => ParityErrorIntErr,
D_IntErr_Out => D_IntErr_Out,
DPar_IntErr_OUT => DPar_IntErr_OUT
);
Error_Handler_1 : Error_Handler
port map (
Clk_Int => Clk_Int,
D_Int_In => D_Int_In,
DPar_Int_In => DPar_Int_In,
CPUHalt_OUT_N => CPUHalt_OUT_N,
Reset_OUT_N => Reset_OUT_N,
Reset_Cause => Reset_Cause,
ResetOutDetect => ResetOutDetect,
NoClkDetect => NoClkDetect,
ErrResStatReg_N => ErrResStatReg_N,
Wr_Int_N => Wr_Int_N,
ErrorCtrl => ErrorCtrl,
IUErr_in_N => IUErr_in_N,
IUHWErr_in_N => IUHWErr_in_N,
IUCmpErr_in_N => IUCmpErr_in_N,
FPUHWErr_in_N => FPUHWErr_in_N,
FPUCmpErr_in_N => FPUCmpErr_in_N,
MecHWErr_Int_N => MECHWErr_In_N,
SWHalt_En => SWHalt_En,
SysErr_OUT_N => SysErr_OUT_N,
MecHWErr_OUT_N => MecHWErr_OUT_N,
ErrorReset_N => ErrorReset_N,
ErrorHalt_N => ErrorHalt_N,
D_Error_Out => D_Error_Out,
DPar_Error_Out => DPar_Error_Out,
SysAv_OUT => SysAv_OUT,
Int_MaskErr => Int_MaskErr,
ParityErrorErrHandl => ParityErrorErrHandl
);
end Mini_Spec;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or used without the written --
-- permission of MATRA MARCONI SPACE FRANCE. --
---------------------------------------------------------------------------
-- Title: power down control
-- File name: pwrdown.vhd
-- VHDL unit: PowerDownModeCtl
-- Purpose and functionality: (Text)
-- Reference: (RDx)
-- Analysis Dependencies: (N/A)
-- Limitations: (N/A)
-- Fidelity: (N/A)
-- Discrepancies: (N/A)
-- Usage: (N/A)
-- I/O: (N/A)
-- Operations: (N/A)
-- Assertions: (N/A)
-- Development Platform: (N/A)
-- Analyzer: (No Dependencies)
-- Synthesis: (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included) --
---------------------------------------------------------------------------
-- Version No: Author: Modification Date: Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A Remi CISSOU 1996-04-22 New issue
--
---------------------------------------------------------------------------
--
library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
entity PowerDownModeCtl is
port (
Reset_Int_N : in Std_Logic;
Clk_Int : in Std_Logic;
Wr_Int_N : in Std_Logic;
PwrDReg_N : in Std_Logic;
PowerDownEn : in Std_Logic;
AnyInterrupt : in Std_Logic;
PowerDown : out Std_Logic
);
end PowerDownModeCtl;
architecture Mini_Spec of PowerDownModeCtl is
begin
PowerDownGenerator: process(Reset_Int_N, Clk_Int)
begin
if Reset_Int_N = '0' then
PowerDown <= '0';
elsif Clk_Int'event and Clk_Int = '0' then
--Powerdown disable
if (AnyInterrupt = '1') then
PowerDown <= '0';
--Powerdown enable
elsif (PwrDReg_N = '0') and (PowerDownEn = '1') and
(Wr_Int_N = '0') then
PowerDown <= '1';
end if;
end if;
end process;
end Mini_Spec;
---------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE --
---------------------------------------------------------------------------
-- The ownership and copyright of this document belong to --
-- MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied, --
-- altered or
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