Ports:

Port Name	Type	Usage	Description	Comments
DataA	I	Required	DataB is compared to this.	Vector, LPM_Width wide
DataB	I	Required	This is compared to DataA	Vector, LPM_Width wide
AGB	O	Note 1	High (1) if DataA > DataB
AGEB	O	Note 1	High (1) if DataA > = DataB
AEB	O	Note 1	High (1) if DataA = DataB
ANEB	O	Note 1	High (1) if DataA ! = DataB
ALB	O	Note 1	High (1) if DataA < DataB
ALEB	O	Note 1	High (1) if DataA < = DataB
Clock	I	Optional	Clock for pipelined usage	Note 2
Aclr	I	Optional	Asynchronous Clear	Note 3

Note 1: At least one of the 6 output ports must be connected.

Note 2: The clock port provides for pipelined operation of the LPM_MUX. If a latency other 0 (default value) is specified, then the clock port must be connected.

Note 3: The pipelined initializes to undefined. The Aclr port may be used at any time to reset the pipeline to all 0's asynchronously to clock.

Properties

Property	Usage	Value	Comments
LPM_Width	Required	LPM Value > = 0	Width of DataA and DataB
LPM_Representation	Optional	UNSIGNED or SIGNED	Default is UNSIGNED.
LPM_Pipeline	Optional	LPM Value 0	Default is 0 - non-pipelined

Functions

Signed or unsigned comparison of the value represented by DataA versus the value represented by DataB. Note that:

AEB = ~ANEB

ALB = ~AGEB

AGB = ~ALEB

Copyright © 1998 University of Manchester