Pin to Pin delay Example

Input pad through combinational element through output pad

From timing model:

TINYL + TIRD1 + TPD + TRD1 + TDLH

1.16ns + 2.24 ns + 1.55ns + 0.8 ns + 2.7 ns

Pin to Pin = 8.45 ns

TINYL Input pad to Y low

TIRD1 Input Fanout 1 routing delay (higher the fanout, longer the delay)

TPD Logic module prop delay

TRD1 Output Fanout 1 routing delay

TDLH Data to Pad high delay

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