SS30 68HC11F1 Co-processor
SS30 based 68HC11 for use in a SWTPC. The board is designed
using readily available junkbox components.
The board uses 4 x 32K x 8 Cache RAM chips out of an old 486 mapped at $0000
- $7FFF.
I/O port Pins PG0 and PG1 select which 32K Bank of RAM to use.
An extra 32K x 8 RAM sits at $8000 - $FFFF and is selected by the CSGEN*
General Chip select decoder
A 64Kbyte EPROM (27512) is selected with the CSPROG* output and may be used
as a ROM library.
Typically only the top 4K bytes would be selected from $F000 - $FFFF and
would overlay the top RAM chip.
The bottom RAM pages are perminantly mapped with the current design, so you
can really only access the top 32K of the 27512.
The HC11 communicates with the SWTPC via four latches providing two x 2 way
8 bit ports.
Typically one port would be used as a data port and the other as a control
port.
Two 74HC138 decoders are used to decode the control and data register clocks
and output enables.
Data would be clocked into that data port from the SWTPC and a byte written
to the control register to indicate the data is valid. The HC11 might read
the data and acknowledge by writing a byte to its control register.
A write from the SWTPC to its control register generates an interrupt request
to the HC11, and similarly a write by the HC11 to the SWTPC generates in
interrupt to the SWTPC.
There are two 20 pin headers. One is used for the 8 Analog to Digital Converter
inputs.
The other 20 pin connector is used for a general purpose 8 bit data port,
Port A and the SPI interfcae.
A MAX232 chip is used to provide RS232 comms via an asyncronous serial port.
