--
-- Tony Givargis
--

--**************************************************************************--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--**************************************************************************--

entity XS40 is 
	port(rst : in STD_LOGIC;
             clk : in STD_LOGIC;
             led : out STD_LOGIC_VECTOR (6 downto 0);
             pcp : in STD_LOGIC_VECTOR (3 downto 0));
end XS40;

--**************************************************************************--

architecture XS40_ARCH of XS40 is

	component WRLED
		port(val : in UNSIGNED (3 downto 0);
		     led : out STD_LOGIC_VECTOR (6 downto 0));
	end component;

	constant C0_4 : UNSIGNED (3 downto 0) := "0000";

	signal val : UNSIGNED (3 downto 0);	
begin
	U1 : WRLED port map(VAL, LED);
	
	process(rst, clk)
	begin
		if( rst = '0' ) then

			val <= C0_4;
		elsif( clk'event and clk = '1' ) then

			val <= UNSIGNED(pcp);
		end if;
	end process;
end XS40_ARCH;


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