Northeastern University, Electrical and Computer Engineering Department NU: ECE 3401 - NTU: DS 765-F Digital System Design with Hardware Description Languages Summer 1998 4:00-5:40 PM Tue, Thr Dr. Zainalabedin Navabi
CONTENTS:
The course covers the standard VHDL hardware description language. Using this language for design, description and synthesis of hardware is emphasized. We will begin with a general overview of the language. Timing issues in a hardware language and concurrency will be discussed next. Description of hardware at three levels of abstraction will be discussed. These levels are structural, dataflow and behavioral and will be discussed in this order. This will be followed by presenting VHDL 1993 new features and other VHDL related IEEE standards. The course continues with presenting a CPU design process in VHDL. Initially the CPU will be presented. This machine will be described at behavioral level and at the dataflow level for manual design. Next, an overview of synthesis will be given. The CPU will then be rewritten for synthesizability. Generated hardware and various synthesis styles will be discussed. Using VHDL, we will design a Cache controller and peripheral interfaces such as an interrupt controller and a DMA for our example CPU. The completed design illustrates top-down design procedure for a complex design.
Ref1: "VHDL: Analysis and Modeling of Digital Systems," Second Edition, Zainalabedin Navabi, McGraw-Hill Publishing Inc., New York, 1998. Ref2: Lecture notes will be on the Web pages LECTURE 1: CHAPTER 1-2 Introduction, HDLs, Simulation, Synthesis, CAD environments HOMEWORK: -- LECTURE 2: CHAPTER 3-4 VHDL history, evolution, design strategy, levels of abstraction, VHDL overview, the general structure of the language HOMEWORK: -- LECTURE 3: CHAPTER 4 VHDL timing, concurrency, sequentially HOMEWORK: LECTURE 4: CHAPTER 4 VHDL timing, concurrency, sequentially HOMEWORK: LECTURE 5: CHAPTER 5 Structural descriptions in VHDL, Binding alternatives, design of flip-flops, iterative structures HOMEWORK: TBA LECTURE 6: CHAPTER 5-6 Design organization, subprograms, number conversion, packages HOMEWORK: TBA LECTURE 7: CHAPTER 6 Design parametrization, configuration declaration, binding alternatives HOMEWORK: -- LECTURE 8: CHAPTER 7 Types, Arrays, Physical types, overloading HOMEWORK: 6.12 LECTURE 9: CHAPTER 7 Overloading, attributes, user attributes HOMEWORK: -- LECTURE 10: CHAPTER 8 Modeling selection logic, block statements, clocked flip-flops, latches HOMEWORK: 7.8, 7.17, 7.19, 7.20, 7.25, 7.26 LECTURE 11: CHAPTER 8 State machine, multiple active states, open collector gates HOMEWORK: -- LECTURE 12: CHAPTER 9 Process statements, text IO, State machines, HOMEWORK: TBA LECTURE 13: CHAPTER 9 Handshaking, Other forms of state machines, a top-down design HOMEWORK: -- TEST 1 : CHAPTERS 1-8 plus processes and timing; Old Exams are available; Takes up one lecture (14). LECTURE 15: CHAPTER 10 Defining Parwan CPU, timing, utilities, Parwan behavioral description, partitioning, sub-components HOMEWORK: LECTURE 16: CHAPTER 10 Control unit, wiring the machine HOMEWORK: -- LECTURE 17: CHAPTER 10 Complete the description of Parwan, a simple test bench HOMEWORK: LECTURE 18: Appendix B, CHAPTER 11 Synthesis in VHDL, styles, logic units, registers, state machines, CPU peripherals HOMEWORK: -- LECTURE 19: CHAPTER 11 CPU Peripherals HOMEWORK: LECTURE 20: CHAPTER 11 Cache, DMA, Complete system HOMEWORK: --
POLICY:
Texts:
Manuals:
Software manuals will be available in the computer room. If necessary, parts of the manuals will be distributed.
Grading:
Your overall grade will be determined by homeworks, a mid-term exam and a final exam.
Homeworks
20%A
Mid-term Exam
30%
Final Exam
50%
Objective:
Study of VHDL and how it can be used in a digital system design environment. Study and design of a small instruction computer at the Register Transfer Level, using the VHDL language. IO devices and designing them with VHDL.
Assignments:
Several problems will be assigned with each lecture. Homeworks are due a week after they are assigned, and they must be submitted to the TA in the computer room or emailed to the designated TA. A homework not turned in will receive a -10 grade, this translates to a -3% from the overall grade. Reasonably late homeworks will be accepted with a 10% per week penalty.
Midterm:
A midterm will be given after completing the first half of the course. This exam will be open book and reasonable number of references is permitted.
Final:
The Final exam covering the entire course material will be given on the scheduled exam date. Half page cheat-sheet is permitted.
Computer:
The main computers used in this course are the ECE PC computers. These machines are equipped with Model Technology V-System VHDL simulator. Other VHDL simulators that become available will be installed on these same machines.
Attendance:
Attendance is required. Lectures are from the combination of the texts and the notes.
Prerequisites:
The prerequisite material for this course is the material that any Computer Engineering Graduate student should be very good at. This includes a good knowledge of digital circuits, sequential and logic circuit design, MSI parts, general understanding of computer instructions and addressing. You must at least know one high level programming language. Knowledge of computer logic and programming languages is essential for successful completion of this course.
